// Copyright (C) 2017 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License // Subscription Agreement, the Intel Quartus Prime License Agreement, // the Intel FPGA IP License Agreement, or other applicable license // agreement, including, without limitation, that your use is for // the sole purpose of programming logic devices manufactured by // Intel and sold by Intel or its authorized distributors. Please // refer to the applicable agreement for further details. // ***************************************************************************** // This file contains a Verilog test bench with test vectors .The test vectors // are exported from a vector file in the Quartus Waveform Editor and apply to // the top level entity of the current Quartus project .The user can use this // testbench to simulate his design using a third-party simulation tool . // ***************************************************************************** // Generated on "09/26/2023 10:58:00" // Verilog Test Bench (with test vectors) for design : decoder2627 // // Simulation tool : 3rd Party // `timescale 1 ps/ 1 ps module decoder2627_vlg_vec_tst(); // constants // general purpose registers reg A; reg B; // wires wire [3:0] F; // assign statements (if any) decoder2627 i1 ( // port map - connection between master ports and signals/registers .A(A), .B(B), .F(F) ); initial begin #1000000 $finish; end // A always begin A = 1'b0; A = #20000 1'b1; #20000; end // B initial begin repeat(12) begin B = 1'b0; B = #40000 1'b1; # 40000; end B = 1'b0; end endmodule