// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition"

// DATE "09/26/2023 10:58:01"

// 
// Device: Altera EP4CE55F23C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module decoder2627 (
	F,
	B,
	A);
output 	[3:0] F;
input 	B;
input 	A;

// Design Ports Information
// F[3]	=>  Location: PIN_R6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// F[2]	=>  Location: PIN_R5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// F[1]	=>  Location: PIN_P6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// F[0]	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// B	=>  Location: PIN_T4,	 I/O Standard: 2.5 V,	 Current Strength: Default
// A	=>  Location: PIN_V6,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \F[3]~output_o ;
wire \F[2]~output_o ;
wire \F[1]~output_o ;
wire \F[0]~output_o ;
wire \B~input_o ;
wire \A~input_o ;
wire \inst2~0_combout ;
wire \inst2~1_combout ;
wire \inst2~2_combout ;
wire \inst3~combout ;


hard_block auto_generated_inst(
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// Location: IOOBUF_X0_Y4_N23
cycloneive_io_obuf \F[3]~output (
	.i(\inst2~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\F[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \F[3]~output .bus_hold = "false";
defparam \F[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y4_N2
cycloneive_io_obuf \F[2]~output (
	.i(\inst2~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\F[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \F[2]~output .bus_hold = "false";
defparam \F[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y5_N23
cycloneive_io_obuf \F[1]~output (
	.i(\inst2~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\F[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \F[1]~output .bus_hold = "false";
defparam \F[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y4_N16
cycloneive_io_obuf \F[0]~output (
	.i(!\inst3~combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\F[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \F[0]~output .bus_hold = "false";
defparam \F[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X0_Y4_N8
cycloneive_io_ibuf \B~input (
	.i(B),
	.ibar(gnd),
	.o(\B~input_o ));
// synopsys translate_off
defparam \B~input .bus_hold = "false";
defparam \B~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X1_Y0_N22
cycloneive_io_ibuf \A~input (
	.i(A),
	.ibar(gnd),
	.o(\A~input_o ));
// synopsys translate_off
defparam \A~input .bus_hold = "false";
defparam \A~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X1_Y4_N16
cycloneive_lcell_comb \inst2~0 (
// Equation(s):
// \inst2~0_combout  = (\B~input_o  & \A~input_o )

	.dataa(\B~input_o ),
	.datab(gnd),
	.datac(gnd),
	.datad(\A~input_o ),
	.cin(gnd),
	.combout(\inst2~0_combout ),
	.cout());
// synopsys translate_off
defparam \inst2~0 .lut_mask = 16'hAA00;
defparam \inst2~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y4_N10
cycloneive_lcell_comb \inst2~1 (
// Equation(s):
// \inst2~1_combout  = (\B~input_o  & !\A~input_o )

	.dataa(\B~input_o ),
	.datab(gnd),
	.datac(gnd),
	.datad(\A~input_o ),
	.cin(gnd),
	.combout(\inst2~1_combout ),
	.cout());
// synopsys translate_off
defparam \inst2~1 .lut_mask = 16'h00AA;
defparam \inst2~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y4_N4
cycloneive_lcell_comb \inst2~2 (
// Equation(s):
// \inst2~2_combout  = (!\B~input_o  & \A~input_o )

	.dataa(\B~input_o ),
	.datab(gnd),
	.datac(gnd),
	.datad(\A~input_o ),
	.cin(gnd),
	.combout(\inst2~2_combout ),
	.cout());
// synopsys translate_off
defparam \inst2~2 .lut_mask = 16'h5500;
defparam \inst2~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y4_N14
cycloneive_lcell_comb inst3(
// Equation(s):
// \inst3~combout  = (\B~input_o ) # (\A~input_o )

	.dataa(\B~input_o ),
	.datab(gnd),
	.datac(gnd),
	.datad(\A~input_o ),
	.cin(gnd),
	.combout(\inst3~combout ),
	.cout());
// synopsys translate_off
defparam inst3.lut_mask = 16'hFFAA;
defparam inst3.sum_lutc_input = "datac";
// synopsys translate_on

assign F[3] = \F[3]~output_o ;

assign F[2] = \F[2]~output_o ;

assign F[1] = \F[1]~output_o ;

assign F[0] = \F[0]~output_o ;

endmodule

module hard_block (

	devpor,
	devclrn,
	devoe);

// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_D1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_K2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_K1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_K22,	 I/O Standard: 2.5 V,	 Current Strength: 8mA

input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

wire \~ALTERA_ASDO_DATA1~~padout ;
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
wire \~ALTERA_DATA0~~padout ;
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
wire \~ALTERA_DATA0~~ibuf_o ;


endmodule