Determining the location of the ModelSim executable... Using: c:/intelfpga_lite/17.1/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder24 -c decoder24 --vector_source="D:/1.decoder24/Waveform.vwf" --testbench_file="D:/1.decoder24/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Sep 26 10:57:59 2023 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder24 -c decoder24 --vector_source=D:/1.decoder24/Waveform.vwf --testbench_file=D:/1.decoder24/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="D:/1.decoder24/simulation/qsim/" decoder24 -c decoder24 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Sep 26 10:58:00 2023 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=D:/1.decoder24/simulation/qsim/ decoder24 -c decoder24 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file decoder24.vo in folder "D:/1.decoder24/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4634 megabytes Info: Processing ended: Tue Sep 26 10:58:01 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** D:/1.decoder24/simulation/qsim/decoder24.do generated. Completed successfully. **** Running the ModelSim simulation **** c:/intelfpga_lite/17.1/modelsim_ase/win32aloem//vsim -c -do decoder24.do Reading C:/intelFPGA_lite/17.1/modelsim_ase/tcl/vsim/pref.tcl # 10.5b # do decoder24.do # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:58:01 on Sep 26,2023 # vlog -work work decoder24.vo # -- Compiling module decoder2627 # -- Compiling module hard_block # # Top level modules: # decoder2627 # End time: 10:58:01 on Sep 26,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:58:01 on Sep 26,2023 # vlog -work work Waveform.vwf.vt # -- Compiling module decoder2627_vlg_vec_tst # # Top level modules: # decoder2627_vlg_vec_tst # End time: 10:58:01 on Sep 26,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder2627_vlg_vec_tst # Start time: 10:58:01 on Sep 26,2023 # Loading work.decoder2627_vlg_vec_tst # Loading work.decoder2627 # Loading work.hard_block # Loading cycloneive_ver.cycloneive_io_obuf # Loading cycloneive_ver.cycloneive_io_ibuf # Loading cycloneive_ver.cycloneive_lcell_comb # after#26 # ** Note: $finish : Waveform.vwf.vt(46) # Time: 1 us Iteration: 0 Instance: /decoder2627_vlg_vec_tst # End time: 10:58:01 on Sep 26,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Completed successfully. **** Converting ModelSim VCD to vector waveform **** Reading D:/1.decoder24/Waveform.vwf... Reading D:/1.decoder24/simulation/qsim/decoder24.msim.vcd... Processing channel transitions... Writing the resulting VWF to D:/1.decoder24/simulation/qsim/decoder24_20230926105801.sim.vwf Finished VCD to VWF conversion. Completed successfully. All completed.