// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/09/2023 21:53:32"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          count2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module count2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg ACLR;
reg ALOAD;
reg CLK;
reg [7:0] data;
// wires                                               
wire [7:0] q;

// assign statements (if any)                          
count2627 i1 (
// port map - connection between master ports and signals/registers   
	.ACLR(ACLR),
	.ALOAD(ALOAD),
	.CLK(CLK),
	.data(data),
	.q(q)
);
initial 
begin 
#100000 $finish;
end 

// CLK
always
begin
	CLK = 1'b0;
	CLK = #5000 1'b1;
	#5000;
end 

// ACLR
initial
begin
	ACLR = 1'b0;
	ACLR = #20000 1'b1;
	ACLR = #20000 1'b0;
end 

// ALOAD
initial
begin
	ALOAD = 1'b1;
	ALOAD = #30000 1'b0;
	ALOAD = #10000 1'b1;
	ALOAD = #20000 1'b0;
end 
// data[ 7 ]
initial
begin
	data[7] = 1'b0;
	data[7] = #40000 1'b1;
	data[7] = #10000 1'b0;
end 
// data[ 6 ]
initial
begin
	data[6] = 1'b0;
end 
// data[ 5 ]
initial
begin
	data[5] = 1'b0;
end 
// data[ 4 ]
initial
begin
	data[4] = 1'b0;
	data[4] = #20000 1'b1;
	data[4] = #20000 1'b0;
end 
// data[ 3 ]
initial
begin
	data[3] = 1'b0;
end 
// data[ 2 ]
initial
begin
	repeat(2)
	begin
		data[2] = 1'b0;
		data[2] = #10000 1'b1;
		# 10000;
	end
	data[2] = 1'b0;
end 
// data[ 1 ]
initial
begin
	data[1] = 1'b0;
end 
// data[ 0 ]
initial
begin
	repeat(5)
	begin
		data[0] = 1'b0;
		data[0] = #5000 1'b1;
		# 5000;
	end
	data[0] = 1'b0;
end 
endmodule