{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1695695075031 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2017  Intel Corporation. All rights reserved. " "Copyright (C) 2017  Intel Corporation. All rights reserved." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions  " "Your use of Intel Corporation's design tools, logic functions " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic  " "and other software and tools, and its AMPP partner logic " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing  " "functions, and any output files from any of the foregoing " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any  " "(including device programming or simulation files), and any " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject  " "associated documentation or information are expressly subject " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License  " "to the terms and conditions of the Intel Program License " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors.  Please " "Intel and sold by Intel or its authorized distributors.  Please" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details. " "refer to the applicable agreement for further details." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 26 10:24:34 2023 " "Processing started: Tue Sep 26 10:24:34 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1695695075031 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1695695075031 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off register -c register --vector_source=F:/quartus/3.register/Waveform.vwf --testbench_file=F:/quartus/3.register/simulation/qsim/Waveform.vwf.vt " "Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off register -c register --vector_source=F:/quartus/3.register/Waveform.vwf --testbench_file=F:/quartus/3.register/simulation/qsim/Waveform.vwf.vt" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1695695075031 ""}
{ "Error" "EQNETO_FAILED_TO_OPEN_PROJ" "register register " "Failed to open project \"register\", revision \"register\"." {  } {  } 0 18650 "Failed to open project \"%1!s!\", revision \"%2!s!\"." 0 0 "EDA Netlist Writer" 0 -1 1695695075031 ""}
{ "Error" "EQEXE_ERROR_COUNT" "EDA Netlist Writer 1  0 s Quartus Prime " "Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4579 " "Peak virtual memory: 4579 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1695695075041 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Sep 26 10:24:35 2023 " "Processing ended: Tue Sep 26 10:24:35 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1695695075041 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1695695075041 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1695695075041 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1695695075041 ""}