# -------------------------------------------------------------------------- # # # Copyright (C) 2023 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details, at # https://fpgasoftware.intel.com/eula. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition # Date created = 09:08:06 September 26, 2023 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # 8-register_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Intel recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE6E22C6 set_global_assignment -name TOP_LEVEL_ENTITY register2627 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.2 set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:08:06 SEPTEMBER 26, 2023" set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V set_global_assignment -name BDF_FILE 273.bdf set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name BDF_FILE register2627.bdf set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top