// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "09/26/2023 11:12:25"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          register2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module register2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg CLK;
reg [7:0] D;
// wires                                               
wire [7:0] Q;

// assign statements (if any)                          
register2627 i1 (
// port map - connection between master ports and signals/registers   
	.CLK(CLK),
	.D(D),
	.Q(Q)
);
initial 
begin 
#256000 $finish;
end 

// CLK
initial
begin
	repeat(170)
	begin
		CLK = 1'b0;
		CLK = #750 1'b1;
		# 750;
	end
	CLK = 1'b0;
	CLK = #750 1'b1;
end 
// D[ 7 ]
always
begin
	D[7] = 1'b0;
	D[7] = #128000 1'b1;
	#128000;
end 
// D[ 6 ]
always
begin
	D[6] = 1'b0;
	D[6] = #64000 1'b1;
	#64000;
end 
// D[ 5 ]
always
begin
	D[5] = 1'b0;
	D[5] = #32000 1'b1;
	#32000;
end 
// D[ 4 ]
always
begin
	D[4] = 1'b0;
	D[4] = #16000 1'b1;
	#16000;
end 
// D[ 3 ]
always
begin
	D[3] = 1'b0;
	D[3] = #8000 1'b1;
	#8000;
end 
// D[ 2 ]
always
begin
	D[2] = 1'b0;
	D[2] = #4000 1'b1;
	#4000;
end 
// D[ 1 ]
always
begin
	D[1] = 1'b0;
	D[1] = #2000 1'b1;
	#2000;
end 
// D[ 0 ]
always
begin
	D[0] = 1'b0;
	D[0] = #1000 1'b1;
	#1000;
end 
endmodule