// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition"

// DATE "09/26/2023 10:20:11"

// 
// Device: Altera EP4CE6E22C6 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module register2627 (
	Q,
	CLK,
	D);
output 	[7:0] Q;
input 	CLK;
input 	[7:0] D;

// Design Ports Information
// Q[7]	=>  Location: PIN_49,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[6]	=>  Location: PIN_67,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[5]	=>  Location: PIN_128,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[4]	=>  Location: PIN_120,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[3]	=>  Location: PIN_111,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[2]	=>  Location: PIN_103,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[1]	=>  Location: PIN_136,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Q[0]	=>  Location: PIN_64,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[7]	=>  Location: PIN_50,	 I/O Standard: 2.5 V,	 Current Strength: Default
// CLK	=>  Location: PIN_23,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[6]	=>  Location: PIN_68,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[5]	=>  Location: PIN_124,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[4]	=>  Location: PIN_115,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[3]	=>  Location: PIN_106,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[2]	=>  Location: PIN_105,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[1]	=>  Location: PIN_135,	 I/O Standard: 2.5 V,	 Current Strength: Default
// D[0]	=>  Location: PIN_65,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \Q[7]~output_o ;
wire \Q[6]~output_o ;
wire \Q[5]~output_o ;
wire \Q[4]~output_o ;
wire \Q[3]~output_o ;
wire \Q[2]~output_o ;
wire \Q[1]~output_o ;
wire \Q[0]~output_o ;
wire \CLK~input_o ;
wire \CLK~inputclkctrl_outclk ;
wire \D[7]~input_o ;
wire \inst|12~q ;
wire \D[6]~input_o ;
wire \inst|13~q ;
wire \D[5]~input_o ;
wire \inst|14~q ;
wire \D[4]~input_o ;
wire \inst|15~q ;
wire \D[3]~input_o ;
wire \inst|16~feeder_combout ;
wire \inst|16~q ;
wire \D[2]~input_o ;
wire \inst|17~feeder_combout ;
wire \inst|17~q ;
wire \D[1]~input_o ;
wire \inst|18~q ;
wire \D[0]~input_o ;
wire \inst|19~feeder_combout ;
wire \inst|19~q ;


hard_block auto_generated_inst(
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// Location: IOOBUF_X13_Y0_N16
cycloneive_io_obuf \Q[7]~output (
	.i(\inst|12~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[7]~output .bus_hold = "false";
defparam \Q[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X30_Y0_N23
cycloneive_io_obuf \Q[6]~output (
	.i(\inst|13~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[6]~output .bus_hold = "false";
defparam \Q[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X16_Y24_N16
cycloneive_io_obuf \Q[5]~output (
	.i(\inst|14~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[5]~output .bus_hold = "false";
defparam \Q[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X23_Y24_N9
cycloneive_io_obuf \Q[4]~output (
	.i(\inst|15~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[4]~output .bus_hold = "false";
defparam \Q[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X30_Y24_N23
cycloneive_io_obuf \Q[3]~output (
	.i(\inst|16~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[3]~output .bus_hold = "false";
defparam \Q[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X34_Y18_N16
cycloneive_io_obuf \Q[2]~output (
	.i(\inst|17~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[2]~output .bus_hold = "false";
defparam \Q[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y24_N9
cycloneive_io_obuf \Q[1]~output (
	.i(\inst|18~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[1]~output .bus_hold = "false";
defparam \Q[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X25_Y0_N2
cycloneive_io_obuf \Q[0]~output (
	.i(\inst|19~q ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Q[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \Q[0]~output .bus_hold = "false";
defparam \Q[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X0_Y11_N8
cycloneive_io_ibuf \CLK~input (
	.i(CLK),
	.ibar(gnd),
	.o(\CLK~input_o ));
// synopsys translate_off
defparam \CLK~input .bus_hold = "false";
defparam \CLK~input .simulate_z_as = "z";
// synopsys translate_on

// Location: CLKCTRL_G2
cycloneive_clkctrl \CLK~inputclkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\CLK~input_o }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\CLK~inputclkctrl_outclk ));
// synopsys translate_off
defparam \CLK~inputclkctrl .clock_type = "global clock";
defparam \CLK~inputclkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: IOIBUF_X13_Y0_N1
cycloneive_io_ibuf \D[7]~input (
	.i(D[7]),
	.ibar(gnd),
	.o(\D[7]~input_o ));
// synopsys translate_off
defparam \D[7]~input .bus_hold = "false";
defparam \D[7]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X13_Y1_N17
dffeas \inst|12 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(gnd),
	.asdata(\D[7]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|12~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|12 .is_wysiwyg = "true";
defparam \inst|12 .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X30_Y0_N8
cycloneive_io_ibuf \D[6]~input (
	.i(D[6]),
	.ibar(gnd),
	.o(\D[6]~input_o ));
// synopsys translate_off
defparam \D[6]~input .bus_hold = "false";
defparam \D[6]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X30_Y1_N17
dffeas \inst|13 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(gnd),
	.asdata(\D[6]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|13~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|13 .is_wysiwyg = "true";
defparam \inst|13 .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X18_Y24_N15
cycloneive_io_ibuf \D[5]~input (
	.i(D[5]),
	.ibar(gnd),
	.o(\D[5]~input_o ));
// synopsys translate_off
defparam \D[5]~input .bus_hold = "false";
defparam \D[5]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X17_Y23_N1
dffeas \inst|14 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(gnd),
	.asdata(\D[5]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|14~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|14 .is_wysiwyg = "true";
defparam \inst|14 .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X28_Y24_N22
cycloneive_io_ibuf \D[4]~input (
	.i(D[4]),
	.ibar(gnd),
	.o(\D[4]~input_o ));
// synopsys translate_off
defparam \D[4]~input .bus_hold = "false";
defparam \D[4]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X25_Y20_N1
dffeas \inst|15 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(gnd),
	.asdata(\D[4]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|15~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|15 .is_wysiwyg = "true";
defparam \inst|15 .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X34_Y20_N8
cycloneive_io_ibuf \D[3]~input (
	.i(D[3]),
	.ibar(gnd),
	.o(\D[3]~input_o ));
// synopsys translate_off
defparam \D[3]~input .bus_hold = "false";
defparam \D[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X33_Y20_N8
cycloneive_lcell_comb \inst|16~feeder (
// Equation(s):
// \inst|16~feeder_combout  = \D[3]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\D[3]~input_o ),
	.cin(gnd),
	.combout(\inst|16~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \inst|16~feeder .lut_mask = 16'hFF00;
defparam \inst|16~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X33_Y20_N9
dffeas \inst|16 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(\inst|16~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|16~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|16 .is_wysiwyg = "true";
defparam \inst|16 .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X34_Y19_N15
cycloneive_io_ibuf \D[2]~input (
	.i(D[2]),
	.ibar(gnd),
	.o(\D[2]~input_o ));
// synopsys translate_off
defparam \D[2]~input .bus_hold = "false";
defparam \D[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X33_Y19_N8
cycloneive_lcell_comb \inst|17~feeder (
// Equation(s):
// \inst|17~feeder_combout  = \D[2]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\D[2]~input_o ),
	.cin(gnd),
	.combout(\inst|17~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \inst|17~feeder .lut_mask = 16'hFF00;
defparam \inst|17~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X33_Y19_N9
dffeas \inst|17 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(\inst|17~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|17~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|17 .is_wysiwyg = "true";
defparam \inst|17 .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X11_Y24_N15
cycloneive_io_ibuf \D[1]~input (
	.i(D[1]),
	.ibar(gnd),
	.o(\D[1]~input_o ));
// synopsys translate_off
defparam \D[1]~input .bus_hold = "false";
defparam \D[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X11_Y23_N1
dffeas \inst|18 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(gnd),
	.asdata(\D[1]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|18~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|18 .is_wysiwyg = "true";
defparam \inst|18 .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X28_Y0_N22
cycloneive_io_ibuf \D[0]~input (
	.i(D[0]),
	.ibar(gnd),
	.o(\D[0]~input_o ));
// synopsys translate_off
defparam \D[0]~input .bus_hold = "false";
defparam \D[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X26_Y1_N24
cycloneive_lcell_comb \inst|19~feeder (
// Equation(s):
// \inst|19~feeder_combout  = \D[0]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\D[0]~input_o ),
	.cin(gnd),
	.combout(\inst|19~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \inst|19~feeder .lut_mask = 16'hFF00;
defparam \inst|19~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X26_Y1_N25
dffeas \inst|19 (
	.clk(\CLK~inputclkctrl_outclk ),
	.d(\inst|19~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\inst|19~q ),
	.prn(vcc));
// synopsys translate_off
defparam \inst|19 .is_wysiwyg = "true";
defparam \inst|19 .power_up = "low";
// synopsys translate_on

assign Q[7] = \Q[7]~output_o ;

assign Q[6] = \Q[6]~output_o ;

assign Q[5] = \Q[5]~output_o ;

assign Q[4] = \Q[4]~output_o ;

assign Q[3] = \Q[3]~output_o ;

assign Q[2] = \Q[2]~output_o ;

assign Q[1] = \Q[1]~output_o ;

assign Q[0] = \Q[0]~output_o ;

endmodule

module hard_block (

	devpor,
	devclrn,
	devoe);

// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_101,	 I/O Standard: 2.5 V,	 Current Strength: 8mA

input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

wire \~ALTERA_ASDO_DATA1~~padout ;
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
wire \~ALTERA_DATA0~~padout ;
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
wire \~ALTERA_DATA0~~ibuf_o ;


endmodule