// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/10/2023 10:01:18"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          alu2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module alu2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg [7:0] A;
reg [7:0] B;
reg CN;
reg M;
reg [3:0] S;
// wires                                               
wire AEQB;
wire CN4;
wire [7:0] F;

// assign statements (if any)                          
alu2627 i1 (
// port map - connection between master ports and signals/registers   
	.A(A),
	.AEQB(AEQB),
	.B(B),
	.CN(CN),
	.CN4(CN4),
	.F(F),
	.M(M),
	.S(S)
);
initial 
begin 
#48000 $finish;
end 
// A[ 7 ]
initial
begin
	A[7] = 1'b0;
end 
// A[ 6 ]
initial
begin
	A[6] = 1'b1;
end 
// A[ 5 ]
initial
begin
	A[5] = 1'b0;
end 
// A[ 4 ]
initial
begin
	A[4] = 1'b0;
end 
// A[ 3 ]
initial
begin
	A[3] = 1'b1;
end 
// A[ 2 ]
initial
begin
	A[2] = 1'b0;
end 
// A[ 1 ]
initial
begin
	A[1] = 1'b1;
end 
// A[ 0 ]
initial
begin
	A[0] = 1'b1;
end 
// B[ 7 ]
initial
begin
	B[7] = 1'b1;
end 
// B[ 6 ]
initial
begin
	B[6] = 1'b1;
end 
// B[ 5 ]
initial
begin
	B[5] = 1'b1;
end 
// B[ 4 ]
initial
begin
	B[4] = 1'b1;
end 
// B[ 3 ]
initial
begin
	B[3] = 1'b1;
end 
// B[ 2 ]
initial
begin
	B[2] = 1'b0;
end 
// B[ 1 ]
initial
begin
	B[1] = 1'b1;
end 
// B[ 0 ]
initial
begin
	B[0] = 1'b0;
end 
// S[ 3 ]
initial
begin
	S[3] = 1'b0;
	S[3] = #8000 1'b1;
	S[3] = #8000 1'b0;
	S[3] = #8000 1'b1;
	S[3] = #8000 1'b0;
	S[3] = #8000 1'b1;
end 
// S[ 2 ]
initial
begin
	repeat(2)
	begin
		S[2] = 1'b0;
		S[2] = #4000 1'b1;
		# 4000;
	end
	repeat(2)
	begin
		S[2] = 1'b0;
		S[2] = #4000 1'b1;
		# 4000;
	end
	repeat(2)
	begin
		S[2] = 1'b0;
		S[2] = #4000 1'b1;
		# 4000;
	end
end 
// S[ 1 ]
initial
begin
	repeat(4)
	begin
		S[1] = 1'b0;
		S[1] = #2000 1'b1;
		# 2000;
	end
	repeat(4)
	begin
		S[1] = 1'b0;
		S[1] = #2000 1'b1;
		# 2000;
	end
	repeat(4)
	begin
		S[1] = 1'b0;
		S[1] = #2000 1'b1;
		# 2000;
	end
end 
// S[ 0 ]
initial
begin
	repeat(8)
	begin
		S[0] = 1'b0;
		S[0] = #1000 1'b1;
		# 1000;
	end
	repeat(8)
	begin
		S[0] = 1'b0;
		S[0] = #1000 1'b1;
		# 1000;
	end
	repeat(8)
	begin
		S[0] = 1'b0;
		S[0] = #1000 1'b1;
		# 1000;
	end
end 

// M
initial
begin
	M = 1'b1;
	M = #16000 1'b0;
end 

// CN
initial
begin
	CN = 1'b0;
	CN = #1000 1'b1;
	CN = #2000 1'b0;
	CN = #4000 1'b1;
	CN = #2000 1'b0;
	CN = #7000 1'b1;
	CN = #16000 1'b0;
end 
endmodule