|bus2627
bus[0] <= lpm_mux0:MUX.result[0]
bus[1] <= lpm_mux0:MUX.result[1]
bus[2] <= lpm_mux0:MUX.result[2]
bus[3] <= lpm_mux0:MUX.result[3]
bus[4] <= lpm_mux0:MUX.result[4]
bus[5] <= lpm_mux0:MUX.result[5]
bus[6] <= lpm_mux0:MUX.result[6]
bus[7] <= lpm_mux0:MUX.result[7]
d0[0] => lpm_mux0:MUX.data0x[0]
d0[1] => lpm_mux0:MUX.data0x[1]
d0[2] => lpm_mux0:MUX.data0x[2]
d0[3] => lpm_mux0:MUX.data0x[3]
d0[4] => lpm_mux0:MUX.data0x[4]
d0[5] => lpm_mux0:MUX.data0x[5]
d0[6] => lpm_mux0:MUX.data0x[6]
d0[7] => lpm_mux0:MUX.data0x[7]
CLK1 => Reg8:R0.CLK
CLK3 => LPM_RAM_DQ:RAM.inclock
we => LPM_RAM_DQ:RAM.we
CLK2 => Reg8:AR.CLK
SELECT[0] => lpm_mux0:MUX.sel[0]
SELECT[1] => lpm_mux0:MUX.sel[1]
led[0] <= Reg8:LED0.Q[0]
led[1] <= Reg8:LED0.Q[1]
led[2] <= Reg8:LED0.Q[2]
led[3] <= Reg8:LED0.Q[3]
led[4] <= Reg8:LED0.Q[4]
led[5] <= Reg8:LED0.Q[5]
led[6] <= Reg8:LED0.Q[6]
led[7] <= Reg8:LED0.Q[7]
CLK4 => Reg8:LED0.CLK


|bus2627|lpm_mux0:MUX
data0x[0] => sub_wire1[0].IN1
data0x[1] => sub_wire1[1].IN1
data0x[2] => sub_wire1[2].IN1
data0x[3] => sub_wire1[3].IN1
data0x[4] => sub_wire1[4].IN1
data0x[5] => sub_wire1[5].IN1
data0x[6] => sub_wire1[6].IN1
data0x[7] => sub_wire1[7].IN1
data1x[0] => sub_wire1[8].IN1
data1x[1] => sub_wire1[9].IN1
data1x[2] => sub_wire1[10].IN1
data1x[3] => sub_wire1[11].IN1
data1x[4] => sub_wire1[12].IN1
data1x[5] => sub_wire1[13].IN1
data1x[6] => sub_wire1[14].IN1
data1x[7] => sub_wire1[15].IN1
data2x[0] => sub_wire1[16].IN1
data2x[1] => sub_wire1[17].IN1
data2x[2] => sub_wire1[18].IN1
data2x[3] => sub_wire1[19].IN1
data2x[4] => sub_wire1[20].IN1
data2x[5] => sub_wire1[21].IN1
data2x[6] => sub_wire1[22].IN1
data2x[7] => sub_wire1[23].IN1
data3x[0] => sub_wire1[24].IN1
data3x[1] => sub_wire1[25].IN1
data3x[2] => sub_wire1[26].IN1
data3x[3] => sub_wire1[27].IN1
data3x[4] => sub_wire1[28].IN1
data3x[5] => sub_wire1[29].IN1
data3x[6] => sub_wire1[30].IN1
data3x[7] => sub_wire1[31].IN1
sel[0] => sel[0].IN1
sel[1] => sel[1].IN1
result[0] <= lpm_mux:LPM_MUX_component.result
result[1] <= lpm_mux:LPM_MUX_component.result
result[2] <= lpm_mux:LPM_MUX_component.result
result[3] <= lpm_mux:LPM_MUX_component.result
result[4] <= lpm_mux:LPM_MUX_component.result
result[5] <= lpm_mux:LPM_MUX_component.result
result[6] <= lpm_mux:LPM_MUX_component.result
result[7] <= lpm_mux:LPM_MUX_component.result


|bus2627|lpm_mux0:MUX|lpm_mux:LPM_MUX_component
data[0][0] => mux_hrc:auto_generated.data[0]
data[0][1] => mux_hrc:auto_generated.data[1]
data[0][2] => mux_hrc:auto_generated.data[2]
data[0][3] => mux_hrc:auto_generated.data[3]
data[0][4] => mux_hrc:auto_generated.data[4]
data[0][5] => mux_hrc:auto_generated.data[5]
data[0][6] => mux_hrc:auto_generated.data[6]
data[0][7] => mux_hrc:auto_generated.data[7]
data[1][0] => mux_hrc:auto_generated.data[8]
data[1][1] => mux_hrc:auto_generated.data[9]
data[1][2] => mux_hrc:auto_generated.data[10]
data[1][3] => mux_hrc:auto_generated.data[11]
data[1][4] => mux_hrc:auto_generated.data[12]
data[1][5] => mux_hrc:auto_generated.data[13]
data[1][6] => mux_hrc:auto_generated.data[14]
data[1][7] => mux_hrc:auto_generated.data[15]
data[2][0] => mux_hrc:auto_generated.data[16]
data[2][1] => mux_hrc:auto_generated.data[17]
data[2][2] => mux_hrc:auto_generated.data[18]
data[2][3] => mux_hrc:auto_generated.data[19]
data[2][4] => mux_hrc:auto_generated.data[20]
data[2][5] => mux_hrc:auto_generated.data[21]
data[2][6] => mux_hrc:auto_generated.data[22]
data[2][7] => mux_hrc:auto_generated.data[23]
data[3][0] => mux_hrc:auto_generated.data[24]
data[3][1] => mux_hrc:auto_generated.data[25]
data[3][2] => mux_hrc:auto_generated.data[26]
data[3][3] => mux_hrc:auto_generated.data[27]
data[3][4] => mux_hrc:auto_generated.data[28]
data[3][5] => mux_hrc:auto_generated.data[29]
data[3][6] => mux_hrc:auto_generated.data[30]
data[3][7] => mux_hrc:auto_generated.data[31]
sel[0] => mux_hrc:auto_generated.sel[0]
sel[1] => mux_hrc:auto_generated.sel[1]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_hrc:auto_generated.result[0]
result[1] <= mux_hrc:auto_generated.result[1]
result[2] <= mux_hrc:auto_generated.result[2]
result[3] <= mux_hrc:auto_generated.result[3]
result[4] <= mux_hrc:auto_generated.result[4]
result[5] <= mux_hrc:auto_generated.result[5]
result[6] <= mux_hrc:auto_generated.result[6]
result[7] <= mux_hrc:auto_generated.result[7]


|bus2627|lpm_mux0:MUX|lpm_mux:LPM_MUX_component|mux_hrc:auto_generated
data[0] => _.IN0
data[0] => _.IN0
data[1] => _.IN0
data[1] => _.IN0
data[2] => _.IN0
data[2] => _.IN0
data[3] => _.IN0
data[3] => _.IN0
data[4] => _.IN0
data[4] => _.IN0
data[5] => _.IN0
data[5] => _.IN0
data[6] => _.IN0
data[6] => _.IN0
data[7] => _.IN0
data[7] => _.IN0
data[8] => _.IN0
data[9] => _.IN0
data[10] => _.IN0
data[11] => _.IN0
data[12] => _.IN0
data[13] => _.IN0
data[14] => _.IN0
data[15] => _.IN0
data[16] => _.IN1
data[16] => _.IN1
data[17] => _.IN1
data[17] => _.IN1
data[18] => _.IN1
data[18] => _.IN1
data[19] => _.IN1
data[19] => _.IN1
data[20] => _.IN1
data[20] => _.IN1
data[21] => _.IN1
data[21] => _.IN1
data[22] => _.IN1
data[22] => _.IN1
data[23] => _.IN1
data[23] => _.IN1
data[24] => _.IN0
data[25] => _.IN0
data[26] => _.IN0
data[27] => _.IN0
data[28] => _.IN0
data[29] => _.IN0
data[30] => _.IN0
data[31] => _.IN0
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0


|bus2627|Reg8:R0
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= 12.DB_MAX_OUTPUT_PORT_TYPE
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => 12.DATAIN


|bus2627|LPM_RAM_DQ:RAM
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]


|bus2627|LPM_RAM_DQ:RAM|altram:sram
we => _.IN0
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
data[6] => altsyncram:ram_block.data_a[6]
data[7] => altsyncram:ram_block.data_a[7]
address[0] => altsyncram:ram_block.address_a[0]
address[1] => altsyncram:ram_block.address_a[1]
address[2] => altsyncram:ram_block.address_a[2]
address[3] => altsyncram:ram_block.address_a[3]
address[4] => altsyncram:ram_block.address_a[4]
address[5] => altsyncram:ram_block.address_a[5]
address[6] => altsyncram:ram_block.address_a[6]
address[7] => altsyncram:ram_block.address_a[7]
clocki => altsyncram:ram_block.clock0
clocko => ~NO_FANOUT~
be => _.IN1
q[0] <= altsyncram:ram_block.q_a[0]
q[1] <= altsyncram:ram_block.q_a[1]
q[2] <= altsyncram:ram_block.q_a[2]
q[3] <= altsyncram:ram_block.q_a[3]
q[4] <= altsyncram:ram_block.q_a[4]
q[5] <= altsyncram:ram_block.q_a[5]
q[6] <= altsyncram:ram_block.q_a[6]
q[7] <= altsyncram:ram_block.q_a[7]


|bus2627|LPM_RAM_DQ:RAM|altram:sram|altsyncram:ram_block
wren_a => altsyncram_ap71:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_ap71:auto_generated.data_a[0]
data_a[1] => altsyncram_ap71:auto_generated.data_a[1]
data_a[2] => altsyncram_ap71:auto_generated.data_a[2]
data_a[3] => altsyncram_ap71:auto_generated.data_a[3]
data_a[4] => altsyncram_ap71:auto_generated.data_a[4]
data_a[5] => altsyncram_ap71:auto_generated.data_a[5]
data_a[6] => altsyncram_ap71:auto_generated.data_a[6]
data_a[7] => altsyncram_ap71:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ap71:auto_generated.address_a[0]
address_a[1] => altsyncram_ap71:auto_generated.address_a[1]
address_a[2] => altsyncram_ap71:auto_generated.address_a[2]
address_a[3] => altsyncram_ap71:auto_generated.address_a[3]
address_a[4] => altsyncram_ap71:auto_generated.address_a[4]
address_a[5] => altsyncram_ap71:auto_generated.address_a[5]
address_a[6] => altsyncram_ap71:auto_generated.address_a[6]
address_a[7] => altsyncram_ap71:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ap71:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ap71:auto_generated.q_a[0]
q_a[1] <= altsyncram_ap71:auto_generated.q_a[1]
q_a[2] <= altsyncram_ap71:auto_generated.q_a[2]
q_a[3] <= altsyncram_ap71:auto_generated.q_a[3]
q_a[4] <= altsyncram_ap71:auto_generated.q_a[4]
q_a[5] <= altsyncram_ap71:auto_generated.q_a[5]
q_a[6] <= altsyncram_ap71:auto_generated.q_a[6]
q_a[7] <= altsyncram_ap71:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|bus2627|LPM_RAM_DQ:RAM|altram:sram|altsyncram:ram_block|altsyncram_ap71:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE


|bus2627|Reg8:AR
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= 12.DB_MAX_OUTPUT_PORT_TYPE
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => 12.DATAIN


|bus2627|Reg8:LED0
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= 12.DB_MAX_OUTPUT_PORT_TYPE
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => 12.DATAIN