--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel --VERSION_BEGIN 17.1 cbx_lpm_mux 2017:10:25:18:06:53:SJ cbx_mgl 2017:10:25:18:08:29:SJ VERSION_END -- Copyright (C) 2017 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details. --synthesis_resources = lut 16 SUBDESIGN mux_hrc ( data[31..0] : input; result[7..0] : output; sel[1..0] : input; ) VARIABLE result_node[7..0] : WIRE; sel_node[1..0] : WIRE; w_data109w[3..0] : WIRE; w_data134w[3..0] : WIRE; w_data159w[3..0] : WIRE; w_data184w[3..0] : WIRE; w_data34w[3..0] : WIRE; w_data4w[3..0] : WIRE; w_data59w[3..0] : WIRE; w_data84w[3..0] : WIRE; BEGIN result[] = result_node[]; result_node[] = ( (((w_data184w[1..1] & sel_node[0..0]) & (! (((w_data184w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data184w[2..2]))))) # ((((w_data184w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data184w[2..2]))) & (w_data184w[3..3] # (! sel_node[0..0])))), (((w_data159w[1..1] & sel_node[0..0]) & (! (((w_data159w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data159w[2..2]))))) # ((((w_data159w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data159w[2..2]))) & (w_data159w[3..3] # (! sel_node[0..0])))), (((w_data134w[1..1] & sel_node[0..0]) & (! (((w_data134w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data134w[2..2]))))) # ((((w_data134w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data134w[2..2]))) & (w_data134w[3..3] # (! sel_node[0..0])))), (((w_data109w[1..1] & sel_node[0..0]) & (! (((w_data109w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data109w[2..2]))))) # ((((w_data109w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data109w[2..2]))) & (w_data109w[3..3] # (! sel_node[0..0])))), (((w_data84w[1..1] & sel_node[0..0]) & (! (((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2]))))) # ((((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2]))) & (w_data84w[3..3] # (! sel_node[0..0])))), (((w_data59w[1..1] & sel_node[0..0]) & (! (((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2]))))) # ((((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2]))) & (w_data59w[3..3] # (! sel_node[0..0])))), (((w_data34w[1..1] & sel_node[0..0]) & (! (((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2]))))) # ((((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2]))) & (w_data34w[3..3] # (! sel_node[0..0])))), (((w_data4w[1..1] & sel_node[0..0]) & (! (((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2]))))) # ((((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2]))) & (w_data4w[3..3] # (! sel_node[0..0]))))); sel_node[] = ( sel[1..0]); w_data109w[] = ( data[28..28], data[20..20], data[12..12], data[4..4]); w_data134w[] = ( data[29..29], data[21..21], data[13..13], data[5..5]); w_data159w[] = ( data[30..30], data[22..22], data[14..14], data[6..6]); w_data184w[] = ( data[31..31], data[23..23], data[15..15], data[7..7]); w_data34w[] = ( data[25..25], data[17..17], data[9..9], data[1..1]); w_data4w[] = ( data[24..24], data[16..16], data[8..8], data[0..0]); w_data59w[] = ( data[26..26], data[18..18], data[10..10], data[2..2]); w_data84w[] = ( data[27..27], data[19..19], data[11..11], data[3..3]); END; --VALID FILE