{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1697517785175 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1697517785184 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 17 12:43:05 2023 " "Processing started: Tue Oct 17 12:43:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1697517785184 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517785184 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bus2627 -c bus2627 " "Command: quartus_map --read_settings_files=on --write_settings_files=off bus2627 -c bus2627" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517785184 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1697517785522 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1697517785522 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_mux0.v 1 1 " "Found 1 design units, including 1 entities, in source file lpm_mux0.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux0 " "Found entity 1: lpm_mux0" { } { { "lpm_mux0.v" "" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697517794940 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517794940 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bus2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bus2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 bus2627 " "Found entity 1: bus2627" { } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697517794943 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517794943 ""} { "Info" "ISGN_START_ELABORATION_TOP" "bus2627 " "Elaborating entity \"bus2627\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1697517794998 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux0 lpm_mux0:MUX " "Elaborating entity \"lpm_mux0\" for hierarchy \"lpm_mux0:MUX\"" { } { { "bus2627.bdf" "MUX" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 184 688 832 296 "MUX" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795024 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux lpm_mux0:MUX\|lpm_mux:LPM_MUX_component " "Elaborating entity \"lpm_mux\" for hierarchy \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\"" { } { { "lpm_mux0.v" "LPM_MUX_component" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 72 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795062 ""} { "Info" "ISGN_ELABORATION_HEADER" "lpm_mux0:MUX\|lpm_mux:LPM_MUX_component " "Elaborated megafunction instantiation \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\"" { } { { "lpm_mux0.v" "" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 72 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795063 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux0:MUX\|lpm_mux:LPM_MUX_component " "Instantiated megafunction \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_size 4 " "Parameter \"lpm_size\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697517795064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MUX " "Parameter \"lpm_type\" = \"LPM_MUX\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697517795064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697517795064 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widths 2 " "Parameter \"lpm_widths\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697517795064 ""} } { { "lpm_mux0.v" "" { Text "D:/Projects/quartus/bus/lpm_mux0.v" 72 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1697517795064 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_hrc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_hrc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_hrc " "Found entity 1: mux_hrc" { } { { "db/mux_hrc.tdf" "" { Text "D:/Projects/quartus/bus/db/mux_hrc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697517795112 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517795112 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_hrc lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\|mux_hrc:auto_generated " "Elaborating entity \"mux_hrc\" for hierarchy \"lpm_mux0:MUX\|lpm_mux:LPM_MUX_component\|mux_hrc:auto_generated\"" { } { { "lpm_mux.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795112 ""} { "Warning" "WSGN_SEARCH_FILE" "reg8.bdf 1 1 " "Using design file reg8.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Reg8 " "Found entity 1: Reg8" { } { { "reg8.bdf" "" { Schematic "D:/Projects/quartus/bus/reg8.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697517795128 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1697517795128 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reg8 Reg8:R0 " "Elaborating entity \"Reg8\" for hierarchy \"Reg8:R0\"" { } { { "bus2627.bdf" "R0" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 80 416 552 176 "R0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795128 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_RAM_DQ LPM_RAM_DQ:RAM " "Elaborating entity \"LPM_RAM_DQ\" for hierarchy \"LPM_RAM_DQ:RAM\"" { } { { "bus2627.bdf" "RAM" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795172 ""} { "Info" "ISGN_ELABORATION_HEADER" "LPM_RAM_DQ:RAM " "Elaborated megafunction instantiation \"LPM_RAM_DQ:RAM\"" { } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795173 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "LPM_RAM_DQ:RAM " "Instantiated megafunction \"LPM_RAM_DQ:RAM\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697517795174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697517795174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 8 " "Parameter \"LPM_WIDTHAD\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1697517795174 ""} } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1697517795174 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram LPM_RAM_DQ:RAM\|altram:sram " "Elaborating entity \"altram\" for hierarchy \"LPM_RAM_DQ:RAM\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795197 ""} { "Warning" "WTDFX_ASSERTION" "altram does not support Cyclone IV E device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone IV E devices " "Assertion warning: altram does not support Cyclone IV E device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone IV E devices" { } { { "altram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 211 2 0 } } { "lpm_ram_dq.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } } } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517795199 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_RAM_DQ:RAM\|altram:sram LPM_RAM_DQ:RAM " "Elaborated megafunction instantiation \"LPM_RAM_DQ:RAM\|altram:sram\", which is child of megafunction instantiation \"LPM_RAM_DQ:RAM\"" { } { { "lpm_ram_dq.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 75 6 0 } } { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795199 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block " "Elaborating entity \"altsyncram\" for hierarchy \"LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\"" { } { { "altram.tdf" "ram_block" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 102 5 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795236 ""} { "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block LPM_RAM_DQ:RAM " "Elaborated megafunction instantiation \"LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\", which is child of megafunction instantiation \"LPM_RAM_DQ:RAM\"" { } { { "altram.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.tdf" 102 5 0 } } { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 336 424 544 448 "RAM" "" } } } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795248 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ap71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ap71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ap71 " "Found entity 1: altsyncram_ap71" { } { { "db/altsyncram_ap71.tdf" "" { Text "D:/Projects/quartus/bus/db/altsyncram_ap71.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1697517795290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517795290 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ap71 LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated " "Elaborating entity \"altsyncram_ap71\" for hierarchy \"LPM_RAM_DQ:RAM\|altram:sram\|altsyncram:ram_block\|altsyncram_ap71:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517795291 ""} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1697517795881 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1697517796334 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1697517796334 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1697517796399 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1697517796399 ""} { "Info" "ICUT_CUT_TM_LCELLS" "40 " "Implemented 40 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1697517796399 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1697517796399 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1697517796399 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4841 " "Peak virtual memory: 4841 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1697517796410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 17 12:43:16 2023 " "Processing ended: Tue Oct 17 12:43:16 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1697517796410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1697517796410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1697517796410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1697517796410 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1697517797735 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1697517797744 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 17 12:43:17 2023 " "Processing started: Tue Oct 17 12:43:17 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1697517797744 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1697517797744 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off bus2627 -c bus2627 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off bus2627 -c bus2627" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1697517797744 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #3" { } { } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1697517797887 ""} { "Info" "0" "" "Project = bus2627" { } { } 0 0 "Project = bus2627" 0 0 "Fitter" 0 0 1697517797889 ""} { "Info" "0" "" "Revision = bus2627" { } { } 0 0 "Revision = bus2627" 0 0 "Fitter" 0 0 1697517797889 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1697517797967 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1697517797969 ""} { "Info" "IMPP_MPP_USER_DEVICE" "bus2627 EP4CE55F23C8 " "Selected device EP4CE55F23C8 for design \"bus2627\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1697517797977 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1697517798037 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1697517798037 ""} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1697517798256 ""} { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1697517798269 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F23C8 " "Device EP4CE15F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1697517798424 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F23C8 " "Device EP4CE40F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1697517798424 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F23C8 " "Device EP4CE30F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1697517798424 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F23C8 " "Device EP4CE75F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1697517798424 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F23C8 " "Device EP4CE115F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1697517798424 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1697517798424 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 246 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1697517798437 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 248 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1697517798437 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 250 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1697517798437 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 252 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1697517798437 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 254 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1697517798437 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1697517798437 ""} { "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1697517798442 ""} { "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1697517798453 ""} { "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "31 31 " "No exact pin location assignment(s) for 31 pins of 31 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1697517798893 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "bus2627.sdc " "Synopsys Design Constraints File file not found: 'bus2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1697517799062 ""} { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1697517799063 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1697517799065 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1697517799065 ""} { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1697517799066 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK1~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node CLK1~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1697517799104 ""} } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 120 120 288 136 "CLK1" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 237 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1697517799104 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK2~input (placed in PIN T2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLK2~input (placed in PIN T2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1697517799104 ""} } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 232 120 288 248 "CLK2" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 240 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1697517799104 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK3~input (placed in PIN T1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node CLK3~input (placed in PIN T1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1697517799104 ""} } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 384 120 288 400 "CLK3" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 239 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1697517799104 ""} { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK4~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node CLK4~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1697517799104 ""} } { { "bus2627.bdf" "" { Schematic "D:/Projects/quartus/bus/bus2627.bdf" { { 544 120 288 560 "CLK4" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/bus/" { { 0 { 0 ""} 0 241 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1697517799104 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1697517799300 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1697517799300 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1697517799301 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1697517799301 ""} { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1697517799302 ""} { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1697517799302 ""} { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1697517799302 ""} { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1697517799302 ""} { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1697517799313 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1697517799313 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1697517799313 ""} { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "27 unused 2.5V 11 16 0 " "Number of I/O pins in group: 27 (unused VREF, 2.5V VCCIO, 11 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1697517799316 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1697517799316 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1697517799316 ""} { "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 28 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 28 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 39 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 41 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 43 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 41 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 38 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 38 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 43 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1697517799317 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1697517799317 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1697517799317 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1697517799345 ""} { "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1697517799358 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1697517800466 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1697517800541 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1697517800566 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1697517803227 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1697517803227 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1697517803387 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X66_Y43 X77_Y53 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X66_Y43 to location X77_Y53" { } { { "loc" "" { Generic "D:/Projects/quartus/bus/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X66_Y43 to location X77_Y53"} { { 12 { 0 ""} 66 43 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1697517804605 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1697517804605 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1697517804983 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1697517804983 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1697517804986 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.20 " "Total time spent on timing analysis during the Fitter is 0.20 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1697517805089 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1697517805096 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1697517805252 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1697517805252 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1697517805385 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1697517805676 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Projects/quartus/bus/output_files/bus2627.fit.smsg " "Generated suppressed messages file D:/Projects/quartus/bus/output_files/bus2627.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1697517805950 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6563 " "Peak virtual memory: 6563 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1697517806196 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 17 12:43:26 2023 " "Processing ended: Tue Oct 17 12:43:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1697517806196 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1697517806196 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1697517806196 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1697517806196 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1697517807211 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1697517807219 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 17 12:43:27 2023 " "Processing started: Tue Oct 17 12:43:27 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1697517807219 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1697517807219 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off bus2627 -c bus2627 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off bus2627 -c bus2627" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1697517807219 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1697517807462 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1697517808483 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1697517808522 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4672 " "Peak virtual memory: 4672 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1697517808689 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 17 12:43:28 2023 " "Processing ended: Tue Oct 17 12:43:28 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1697517808689 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1697517808689 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1697517808689 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1697517808689 ""} { "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1697517809309 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1697517809833 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1697517809842 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 17 12:43:29 2023 " "Processing started: Tue Oct 17 12:43:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1697517809842 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517809842 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta bus2627 -c bus2627 " "Command: quartus_sta bus2627 -c bus2627" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517809842 ""} { "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1697517809960 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810114 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810114 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810161 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810161 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "bus2627.sdc " "Synopsys Design Constraints File file not found: 'bus2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810379 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810380 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK3 CLK3 " "create_clock -period 1.000 -name CLK3 CLK3" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1697517810381 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK2 CLK2 " "create_clock -period 1.000 -name CLK2 CLK2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1697517810381 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK1 CLK1 " "create_clock -period 1.000 -name CLK1 CLK1" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1697517810381 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK4 CLK4 " "create_clock -period 1.000 -name CLK4 CLK4" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1697517810381 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810381 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810383 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810384 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1697517810384 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1697517810392 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1697517810405 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810405 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -5.465 " "Worst-case setup slack is -5.465" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.465 -40.468 CLK4 " " -5.465 -40.468 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.387 -38.659 CLK2 " " -5.387 -38.659 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.386 -38.658 CLK1 " " -5.386 -38.658 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.055 -5.659 CLK3 " " -5.055 -5.659 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810407 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810407 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.807 " "Worst-case hold slack is 0.807" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.807 0.000 CLK3 " " 0.807 0.000 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.883 0.000 CLK1 " " 0.883 0.000 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.952 0.000 CLK2 " " 0.952 0.000 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.235 0.000 CLK4 " " 1.235 0.000 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810409 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810412 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810414 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.201 " "Worst-case minimum pulse width slack is -3.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810416 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810416 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.201 -12.603 CLK3 " " -3.201 -12.603 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810416 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 CLK1 " " -3.000 -14.896 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810416 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 CLK2 " " -3.000 -14.896 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810416 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 CLK4 " " -3.000 -14.896 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810416 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810416 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1697517810455 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810471 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810642 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810687 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1697517810691 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810691 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -4.974 " "Worst-case setup slack is -4.974" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.974 -36.733 CLK4 " " -4.974 -36.733 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.876 -34.902 CLK2 " " -4.876 -34.902 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.874 -34.894 CLK1 " " -4.874 -34.894 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.641 -5.209 CLK3 " " -4.641 -5.209 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810693 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810693 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.733 " "Worst-case hold slack is 0.733" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.733 0.000 CLK3 " " 0.733 0.000 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.802 0.000 CLK1 " " 0.802 0.000 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.869 0.000 CLK2 " " 0.869 0.000 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.089 0.000 CLK4 " " 1.089 0.000 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810696 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810696 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810699 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810701 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.201 " "Worst-case minimum pulse width slack is -3.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.201 -12.603 CLK3 " " -3.201 -12.603 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 CLK1 " " -3.000 -14.896 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 CLK2 " " -3.000 -14.896 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -14.896 CLK4 " " -3.000 -14.896 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810703 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810703 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1697517810741 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810829 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1697517810830 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810830 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.596 " "Worst-case setup slack is -1.596" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810833 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810833 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.596 -11.390 CLK4 " " -1.596 -11.390 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810833 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.571 -10.605 CLK2 " " -1.571 -10.605 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810833 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.568 -10.600 CLK1 " " -1.568 -10.600 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810833 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.422 -1.422 CLK3 " " -1.422 -1.422 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810833 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810833 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.276 " "Worst-case hold slack is 0.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810837 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810837 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.276 0.000 CLK3 " " 0.276 0.000 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810837 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.314 0.000 CLK1 " " 0.314 0.000 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810837 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.371 0.000 CLK2 " " 0.371 0.000 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810837 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.469 0.000 CLK4 " " 0.469 0.000 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810837 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810837 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810840 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810842 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810844 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810844 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -11.472 CLK2 " " -3.000 -11.472 CLK2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810844 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -11.464 CLK1 " " -3.000 -11.464 CLK1 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810844 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -11.436 CLK4 " " -3.000 -11.436 CLK4 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810844 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -6.364 CLK3 " " -3.000 -6.364 CLK3 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1697517810844 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517810844 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517811167 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517811167 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4929 " "Peak virtual memory: 4929 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1697517811208 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 17 12:43:31 2023 " "Processing ended: Tue Oct 17 12:43:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1697517811208 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1697517811208 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1697517811208 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517811208 ""} { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus Prime Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1697517811895 ""}