|mux21a2627
PC_B <= decodeb:inst5.PC_B
M[0] <= lpm_rom0:inst9.q[0]
M[1] <= lpm_rom0:inst9.q[1]
M[2] <= lpm_rom0:inst9.q[2]
M[3] <= lpm_rom0:inst9.q[3]
M[4] <= lpm_rom0:inst9.q[4]
M[5] <= lpm_rom0:inst9.q[5]
M[6] <= lpm_rom0:inst9.q[6]
M[7] <= lpm_rom0:inst9.q[7]
M[8] <= lpm_rom0:inst9.q[8]
M[9] <= lpm_rom0:inst9.q[9]
M[10] <= lpm_rom0:inst9.q[10]
M[11] <= lpm_rom0:inst9.q[11]
M[12] <= lpm_rom0:inst9.q[12]
M[13] <= lpm_rom0:inst9.q[13]
M[14] <= lpm_rom0:inst9.q[14]
M[15] <= lpm_rom0:inst9.q[15]
M[16] <= lpm_rom0:inst9.q[16]
M[17] <= lpm_rom0:inst9.q[17]
M[18] <= lpm_rom0:inst9.q[18]
M[19] <= lpm_rom0:inst9.q[19]
M[20] <= lpm_rom0:inst9.q[20]
M[21] <= lpm_rom0:inst9.q[21]
M[22] <= lpm_rom0:inst9.q[22]
M[23] <= lpm_rom0:inst9.q[23]
T1 <= Timing:inst1.T1
CLK1 => Timing:inst1.CLK1
STEP => Timing:inst1.RST1
uaddr[0] <= uARReg:inst2.q[1]
uaddr[1] <= uARReg:inst2.q[2]
uaddr[2] <= uARReg:inst2.q[3]
uaddr[3] <= uARReg:inst2.q[4]
uaddr[4] <= uARReg:inst2.q[5]
uaddr[5] <= uARReg:inst2.q[6]
RST1 => uARReg:inst2.CLR
RST1 => lpm_counter0:_PC.aclr
T2 <= Timing:inst1.T2
T3 <= Timing:inst1.T3
d0[0] => lpm_mux1:inst21.data0x[0]
d0[0] => inst31[0].DATAIN
d0[1] => lpm_mux1:inst21.data0x[1]
d0[1] => inst31[1].DATAIN
d0[2] => lpm_mux1:inst21.data0x[2]
d0[2] => inst31[2].DATAIN
d0[3] => lpm_mux1:inst21.data0x[3]
d0[3] => inst31[3].DATAIN
d0[4] => lpm_mux1:inst21.data0x[4]
d0[4] => inst31[4].DATAIN
d0[5] => lpm_mux1:inst21.data0x[5]
d0[5] => inst31[5].DATAIN
d0[6] => lpm_mux1:inst21.data0x[6]
d0[6] => inst31[6].DATAIN
d0[7] => lpm_mux1:inst21.data0x[7]
d0[7] => inst31[7].DATAIN
T4 <= Timing:inst1.T4
LDAR <= decodea:inst6.LDAR
PC[0] <= lpm_counter0:_PC.q[0]
PC[1] <= lpm_counter0:_PC.q[1]
PC[2] <= lpm_counter0:_PC.q[2]
PC[3] <= lpm_counter0:_PC.q[3]
PC[4] <= lpm_counter0:_PC.q[4]
PC[5] <= lpm_counter0:_PC.q[5]
PC[6] <= lpm_counter0:_PC.q[6]
PC[7] <= lpm_counter0:_PC.q[7]
LDPC <= decodec:inst7.LDPC
I[0] <= Reg8:_IR.Q[0]
I[1] <= Reg8:_IR.Q[1]
I[2] <= Reg8:_IR.Q[2]
I[3] <= Reg8:_IR.Q[3]
I[4] <= Reg8:_IR.Q[4]
I[5] <= Reg8:_IR.Q[5]
I[6] <= Reg8:_IR.Q[6]
I[7] <= Reg8:_IR.Q[7]
RAM_B <= decode2_4:inst34.Y[1]
SW_B <= decode2_4:inst34.Y[0]
SWA => uControl:inst.SWA
SWB => uControl:inst.SWB
LED_B <= decode2_4:inst34.Y[2]
bus[0] <= lpm_mux1:inst21.result[0]
bus[1] <= lpm_mux1:inst21.result[1]
bus[2] <= lpm_mux1:inst21.result[2]
bus[3] <= lpm_mux1:inst21.result[3]
bus[4] <= lpm_mux1:inst21.result[4]
bus[5] <= lpm_mux1:inst21.result[5]
bus[6] <= lpm_mux1:inst21.result[6]
bus[7] <= lpm_mux1:inst21.result[7]
in[0] <= inst31[0].DB_MAX_OUTPUT_PORT_TYPE
in[1] <= inst31[1].DB_MAX_OUTPUT_PORT_TYPE
in[2] <= inst31[2].DB_MAX_OUTPUT_PORT_TYPE
in[3] <= inst31[3].DB_MAX_OUTPUT_PORT_TYPE
in[4] <= inst31[4].DB_MAX_OUTPUT_PORT_TYPE
in[5] <= inst31[5].DB_MAX_OUTPUT_PORT_TYPE
in[6] <= inst31[6].DB_MAX_OUTPUT_PORT_TYPE
in[7] <= inst31[7].DB_MAX_OUTPUT_PORT_TYPE
led[0] <= Reg8:_LED_OUT.Q[0]
led[1] <= Reg8:_LED_OUT.Q[1]
led[2] <= Reg8:_LED_OUT.Q[2]
led[3] <= Reg8:_LED_OUT.Q[3]
led[4] <= Reg8:_LED_OUT.Q[4]
led[5] <= Reg8:_LED_OUT.Q[5]
led[6] <= Reg8:_LED_OUT.Q[6]
led[7] <= Reg8:_LED_OUT.Q[7]


|mux21a2627|decodeb:inst5
ALU_B <= inst3.DB_MAX_OUTPUT_PORT_TYPE
A => inst3.IN0
A => inst14.IN0
A => inst.IN0
A => inst2.IN0
B => inst15.IN0
B => inst4.IN1
B => inst1.IN1
B => inst2.IN1
C => inst3.IN2
C => inst4.IN2
C => inst16.IN0
PC_B <= inst4.DB_MAX_OUTPUT_PORT_TYPE
R0_B <= inst.DB_MAX_OUTPUT_PORT_TYPE
R1_B <= inst1.DB_MAX_OUTPUT_PORT_TYPE
R2_B <= inst2.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|lpm_rom0:inst9
q[0] <= LPM_ROM:inst.q[0]
q[1] <= LPM_ROM:inst.q[1]
q[2] <= LPM_ROM:inst.q[2]
q[3] <= LPM_ROM:inst.q[3]
q[4] <= LPM_ROM:inst.q[4]
q[5] <= LPM_ROM:inst.q[5]
q[6] <= LPM_ROM:inst.q[6]
q[7] <= LPM_ROM:inst.q[7]
q[8] <= LPM_ROM:inst.q[8]
q[9] <= LPM_ROM:inst.q[9]
q[10] <= LPM_ROM:inst.q[10]
q[11] <= LPM_ROM:inst.q[11]
q[12] <= LPM_ROM:inst.q[12]
q[13] <= LPM_ROM:inst.q[13]
q[14] <= LPM_ROM:inst.q[14]
q[15] <= LPM_ROM:inst.q[15]
q[16] <= LPM_ROM:inst.q[16]
q[17] <= LPM_ROM:inst.q[17]
q[18] <= LPM_ROM:inst.q[18]
q[19] <= LPM_ROM:inst.q[19]
q[20] <= LPM_ROM:inst.q[20]
q[21] <= LPM_ROM:inst.q[21]
q[22] <= LPM_ROM:inst.q[22]
q[23] <= LPM_ROM:inst.q[23]
clock => LPM_ROM:inst.inclock
address[0] => LPM_ROM:inst.address[0]
address[1] => LPM_ROM:inst.address[1]
address[2] => LPM_ROM:inst.address[2]
address[3] => LPM_ROM:inst.address[3]
address[4] => LPM_ROM:inst.address[4]
address[5] => LPM_ROM:inst.address[5]


|mux21a2627|lpm_rom0:inst9|LPM_ROM:inst
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
inclock => altrom:srom.clocki
outclock => ~NO_FANOUT~
memenab => otri[23].OE
memenab => otri[22].OE
memenab => otri[21].OE
memenab => otri[20].OE
memenab => otri[19].OE
memenab => otri[18].OE
memenab => otri[17].OE
memenab => otri[16].OE
memenab => otri[15].OE
memenab => otri[14].OE
memenab => otri[13].OE
memenab => otri[12].OE
memenab => otri[11].OE
memenab => otri[10].OE
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= otri[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= otri[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= otri[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= otri[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= otri[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= otri[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= otri[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= otri[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= otri[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= otri[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= otri[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= otri[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= otri[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= otri[23].DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|lpm_rom0:inst9|LPM_ROM:inst|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
clocki => altsyncram:rom_block.clock0
clocko => ~NO_FANOUT~
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]
q[7] <= altsyncram:rom_block.q_a[7]
q[8] <= altsyncram:rom_block.q_a[8]
q[9] <= altsyncram:rom_block.q_a[9]
q[10] <= altsyncram:rom_block.q_a[10]
q[11] <= altsyncram:rom_block.q_a[11]
q[12] <= altsyncram:rom_block.q_a[12]
q[13] <= altsyncram:rom_block.q_a[13]
q[14] <= altsyncram:rom_block.q_a[14]
q[15] <= altsyncram:rom_block.q_a[15]
q[16] <= altsyncram:rom_block.q_a[16]
q[17] <= altsyncram:rom_block.q_a[17]
q[18] <= altsyncram:rom_block.q_a[18]
q[19] <= altsyncram:rom_block.q_a[19]
q[20] <= altsyncram:rom_block.q_a[20]
q[21] <= altsyncram:rom_block.q_a[21]
q[22] <= altsyncram:rom_block.q_a[22]
q[23] <= altsyncram:rom_block.q_a[23]


|mux21a2627|lpm_rom0:inst9|LPM_ROM:inst|altrom:srom|altsyncram:rom_block
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_a[16] => ~NO_FANOUT~
data_a[17] => ~NO_FANOUT~
data_a[18] => ~NO_FANOUT~
data_a[19] => ~NO_FANOUT~
data_a[20] => ~NO_FANOUT~
data_a[21] => ~NO_FANOUT~
data_a[22] => ~NO_FANOUT~
data_a[23] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_od01:auto_generated.address_a[0]
address_a[1] => altsyncram_od01:auto_generated.address_a[1]
address_a[2] => altsyncram_od01:auto_generated.address_a[2]
address_a[3] => altsyncram_od01:auto_generated.address_a[3]
address_a[4] => altsyncram_od01:auto_generated.address_a[4]
address_a[5] => altsyncram_od01:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_od01:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_od01:auto_generated.q_a[0]
q_a[1] <= altsyncram_od01:auto_generated.q_a[1]
q_a[2] <= altsyncram_od01:auto_generated.q_a[2]
q_a[3] <= altsyncram_od01:auto_generated.q_a[3]
q_a[4] <= altsyncram_od01:auto_generated.q_a[4]
q_a[5] <= altsyncram_od01:auto_generated.q_a[5]
q_a[6] <= altsyncram_od01:auto_generated.q_a[6]
q_a[7] <= altsyncram_od01:auto_generated.q_a[7]
q_a[8] <= altsyncram_od01:auto_generated.q_a[8]
q_a[9] <= altsyncram_od01:auto_generated.q_a[9]
q_a[10] <= altsyncram_od01:auto_generated.q_a[10]
q_a[11] <= altsyncram_od01:auto_generated.q_a[11]
q_a[12] <= altsyncram_od01:auto_generated.q_a[12]
q_a[13] <= altsyncram_od01:auto_generated.q_a[13]
q_a[14] <= altsyncram_od01:auto_generated.q_a[14]
q_a[15] <= altsyncram_od01:auto_generated.q_a[15]
q_a[16] <= altsyncram_od01:auto_generated.q_a[16]
q_a[17] <= altsyncram_od01:auto_generated.q_a[17]
q_a[18] <= altsyncram_od01:auto_generated.q_a[18]
q_a[19] <= altsyncram_od01:auto_generated.q_a[19]
q_a[20] <= altsyncram_od01:auto_generated.q_a[20]
q_a[21] <= altsyncram_od01:auto_generated.q_a[21]
q_a[22] <= altsyncram_od01:auto_generated.q_a[22]
q_a[23] <= altsyncram_od01:auto_generated.q_a[23]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|mux21a2627|lpm_rom0:inst9|LPM_ROM:inst|altrom:srom|altsyncram:rom_block|altsyncram_od01:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
q_a[16] <= ram_block1a16.PORTADATAOUT
q_a[17] <= ram_block1a17.PORTADATAOUT
q_a[18] <= ram_block1a18.PORTADATAOUT
q_a[19] <= ram_block1a19.PORTADATAOUT
q_a[20] <= ram_block1a20.PORTADATAOUT
q_a[21] <= ram_block1a21.PORTADATAOUT
q_a[22] <= ram_block1a22.PORTADATAOUT
q_a[23] <= ram_block1a23.PORTADATAOUT


|mux21a2627|Timing:inst1
T1 <= inst.DB_MAX_OUTPUT_PORT_TYPE
RST1 => inst.ACLR
RST1 => inst4.ACLR
RST1 => inst3.ACLR
RST1 => inst2.ACLR
RST1 => inst1.ACLR
CLK1 => inst13.IN0
S0 => 21mux:inst10.S
S0 => 21mux:inst9.S
T4 <= inst3.DB_MAX_OUTPUT_PORT_TYPE
T3 <= inst2.DB_MAX_OUTPUT_PORT_TYPE
T2 <= inst1.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|Timing:inst1|21mux:inst10
Y <= 5.DB_MAX_OUTPUT_PORT_TYPE
A => 6.IN0
S => 6.IN1
S => 7.IN1
B => 8.IN0


|mux21a2627|Timing:inst1|21mux:inst9
Y <= 5.DB_MAX_OUTPUT_PORT_TYPE
A => 6.IN0
S => 6.IN1
S => 7.IN1
B => 8.IN0


|mux21a2627|uARReg:inst2
q[1] <= inst40.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= inst41.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= inst42.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= inst43.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= inst44.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= inst45.DB_MAX_OUTPUT_PORT_TYPE
SE[1] => inst40.PRESET
SE[2] => inst41.PRESET
SE[3] => inst42.PRESET
SE[4] => inst43.PRESET
SE[5] => inst44.PRESET
SE[6] => inst45.PRESET
CLR => inst.IN0
D[1] => inst40.DATAIN
D[2] => inst41.DATAIN
D[3] => inst42.DATAIN
D[4] => inst43.DATAIN
D[5] => inst44.DATAIN
D[6] => inst45.DATAIN
CLK => inst40.CLK
CLK => inst41.CLK
CLK => inst42.CLK
CLK => inst45.CLK
CLK => inst44.CLK
CLK => inst43.CLK


|mux21a2627|uControl:inst
SE[1] <= inst10.DB_MAX_OUTPUT_PORT_TYPE
SE[2] <= inst9.DB_MAX_OUTPUT_PORT_TYPE
SE[3] <= inst25.DB_MAX_OUTPUT_PORT_TYPE
SE[4] <= inst24.DB_MAX_OUTPUT_PORT_TYPE
SE[5] <= inst.DB_MAX_OUTPUT_PORT_TYPE
SE[6] <= <VCC>
FZ => inst11.IN0
FC => inst11.IN1
T4 => inst.IN1
T4 => inst24.IN1
T4 => inst25.IN1
T4 => inst26.IN1
T4 => inst27.IN1
T4 => inst28.IN1
T4 => inst29.IN1
T4 => inst30.IN1
T4 => inst31.IN1
P[1] => inst24.IN2
P[1] => inst25.IN2
P[1] => inst26.IN2
P[1] => inst29.IN2
P[2] => inst27.IN2
P[2] => inst30.IN2
P[3] => inst.IN2
P[4] => inst28.IN0
P[4] => inst31.IN0
I[2] => inst30.IN0
I[3] => inst27.IN0
I[4] => inst29.IN0
I[5] => inst26.IN0
I[6] => inst25.IN0
I[7] => inst24.IN0
SWB => inst28.IN2
SWA => inst31.IN2


|mux21a2627|ALU:_ALU_BUSIN1
CN4 <= 74181:inst.CN4
B[0] => 74181:inst2.B0N
B[1] => 74181:inst2.B1N
B[2] => 74181:inst2.B2N
B[3] => 74181:inst2.B3N
B[4] => 74181:inst.B0N
B[5] => 74181:inst.B1N
B[6] => 74181:inst.B2N
B[7] => 74181:inst.B3N
A[0] => 74181:inst2.A0N
A[1] => 74181:inst2.A1N
A[2] => 74181:inst2.A2N
A[3] => 74181:inst2.A3N
A[4] => 74181:inst.A0N
A[5] => 74181:inst.A1N
A[6] => 74181:inst.A2N
A[7] => 74181:inst.A3N
M => 74181:inst.M
M => 74181:inst2.M
CN => 74181:inst2.CN
S[0] => 74181:inst2.S0
S[0] => 74181:inst.S0
S[1] => 74181:inst2.S1
S[1] => 74181:inst.S1
S[2] => 74181:inst2.S2
S[2] => 74181:inst.S2
S[3] => 74181:inst2.S3
S[3] => 74181:inst.S3
AEQB <= inst8.DB_MAX_OUTPUT_PORT_TYPE
F[0] <= 74181:inst2.F0N
F[1] <= 74181:inst2.F1N
F[2] <= 74181:inst2.F2N
F[3] <= 74181:inst2.F3N
F[4] <= 74181:inst.F0N
F[5] <= 74181:inst.F1N
F[6] <= 74181:inst.F2N
F[7] <= 74181:inst.F3N


|mux21a2627|ALU:_ALU_BUSIN1|74181:inst
F1N <= 86.DB_MAX_OUTPUT_PORT_TYPE
A1N => 14.IN0
A1N => 13.IN2
A1N => 44.IN0
S3 => 14.IN1
S3 => 9.IN1
S3 => 24.IN1
S3 => 19.IN1
B1N => 14.IN2
B1N => 28.IN0
B1N => 11.IN1
S2 => 13.IN1
S2 => 8.IN1
S2 => 23.IN1
S2 => 18.IN1
S0 => 11.IN0
S0 => 6.IN0
S0 => 21.IN0
S0 => 16.IN0
S1 => 12.IN1
S1 => 7.IN1
S1 => 22.IN1
S1 => 17.IN1
M => 98.IN0
A0N => 9.IN0
A0N => 8.IN2
A0N => 43.IN0
B0N => 9.IN2
B0N => 27.IN0
B0N => 6.IN1
CN => 66.IN2
CN => 73.IN0
CN => 73.IN3
CN => 69.IN0
CN => 64.IN0
CN => 61.IN4
CN => 61.IN5
AEQB <= 83.DB_MAX_OUTPUT_PORT_TYPE
A3N => 24.IN0
A3N => 23.IN2
A3N => 51.IN0
B3N => 24.IN2
B3N => 25.IN0
B3N => 21.IN1
A2N => 19.IN0
A2N => 18.IN2
A2N => 45.IN0
B2N => 19.IN2
B2N => 31.IN0
B2N => 16.IN1
F2N <= 85.DB_MAX_OUTPUT_PORT_TYPE
F3N <= 84.DB_MAX_OUTPUT_PORT_TYPE
PN <= 60.DB_MAX_OUTPUT_PORT_TYPE
CN4 <= 78.DB_MAX_OUTPUT_PORT_TYPE
GN <= 63.DB_MAX_OUTPUT_PORT_TYPE
F0N <= 87.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|ALU:_ALU_BUSIN1|74181:inst2
F1N <= 86.DB_MAX_OUTPUT_PORT_TYPE
A1N => 14.IN0
A1N => 13.IN2
A1N => 44.IN0
S3 => 14.IN1
S3 => 9.IN1
S3 => 24.IN1
S3 => 19.IN1
B1N => 14.IN2
B1N => 28.IN0
B1N => 11.IN1
S2 => 13.IN1
S2 => 8.IN1
S2 => 23.IN1
S2 => 18.IN1
S0 => 11.IN0
S0 => 6.IN0
S0 => 21.IN0
S0 => 16.IN0
S1 => 12.IN1
S1 => 7.IN1
S1 => 22.IN1
S1 => 17.IN1
M => 98.IN0
A0N => 9.IN0
A0N => 8.IN2
A0N => 43.IN0
B0N => 9.IN2
B0N => 27.IN0
B0N => 6.IN1
CN => 66.IN2
CN => 73.IN0
CN => 73.IN3
CN => 69.IN0
CN => 64.IN0
CN => 61.IN4
CN => 61.IN5
AEQB <= 83.DB_MAX_OUTPUT_PORT_TYPE
A3N => 24.IN0
A3N => 23.IN2
A3N => 51.IN0
B3N => 24.IN2
B3N => 25.IN0
B3N => 21.IN1
A2N => 19.IN0
A2N => 18.IN2
A2N => 45.IN0
B2N => 19.IN2
B2N => 31.IN0
B2N => 16.IN1
F2N <= 85.DB_MAX_OUTPUT_PORT_TYPE
F3N <= 84.DB_MAX_OUTPUT_PORT_TYPE
PN <= 60.DB_MAX_OUTPUT_PORT_TYPE
CN4 <= 78.DB_MAX_OUTPUT_PORT_TYPE
GN <= 63.DB_MAX_OUTPUT_PORT_TYPE
F0N <= 87.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|Reg8:_R1
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~


|mux21a2627|decodea:inst6
LDRI <= inst.DB_MAX_OUTPUT_PORT_TYPE
A => inst.IN0
A => inst14.IN0
A => inst10.IN0
A => inst12.IN0
B => inst15.IN0
B => inst9.IN1
B => inst10.IN1
B => inst13.IN1
C => inst16.IN0
C => inst11.IN2
C => inst12.IN2
C => inst13.IN2
LDDR1 <= inst9.DB_MAX_OUTPUT_PORT_TYPE
LDDR2 <= inst10.DB_MAX_OUTPUT_PORT_TYPE
LDIR <= inst11.DB_MAX_OUTPUT_PORT_TYPE
LOAD <= inst12.DB_MAX_OUTPUT_PORT_TYPE
LDAR <= inst13.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|lpm_mux1:inst21
data0x[0] => sub_wire1[0].IN1
data0x[1] => sub_wire1[1].IN1
data0x[2] => sub_wire1[2].IN1
data0x[3] => sub_wire1[3].IN1
data0x[4] => sub_wire1[4].IN1
data0x[5] => sub_wire1[5].IN1
data0x[6] => sub_wire1[6].IN1
data0x[7] => sub_wire1[7].IN1
data1x[0] => sub_wire1[8].IN1
data1x[1] => sub_wire1[9].IN1
data1x[2] => sub_wire1[10].IN1
data1x[3] => sub_wire1[11].IN1
data1x[4] => sub_wire1[12].IN1
data1x[5] => sub_wire1[13].IN1
data1x[6] => sub_wire1[14].IN1
data1x[7] => sub_wire1[15].IN1
data2x[0] => sub_wire1[16].IN1
data2x[1] => sub_wire1[17].IN1
data2x[2] => sub_wire1[18].IN1
data2x[3] => sub_wire1[19].IN1
data2x[4] => sub_wire1[20].IN1
data2x[5] => sub_wire1[21].IN1
data2x[6] => sub_wire1[22].IN1
data2x[7] => sub_wire1[23].IN1
data3x[0] => sub_wire1[24].IN1
data3x[1] => sub_wire1[25].IN1
data3x[2] => sub_wire1[26].IN1
data3x[3] => sub_wire1[27].IN1
data3x[4] => sub_wire1[28].IN1
data3x[5] => sub_wire1[29].IN1
data3x[6] => sub_wire1[30].IN1
data3x[7] => sub_wire1[31].IN1
data4x[0] => sub_wire1[32].IN1
data4x[1] => sub_wire1[33].IN1
data4x[2] => sub_wire1[34].IN1
data4x[3] => sub_wire1[35].IN1
data4x[4] => sub_wire1[36].IN1
data4x[5] => sub_wire1[37].IN1
data4x[6] => sub_wire1[38].IN1
data4x[7] => sub_wire1[39].IN1
data5x[0] => sub_wire1[40].IN1
data5x[1] => sub_wire1[41].IN1
data5x[2] => sub_wire1[42].IN1
data5x[3] => sub_wire1[43].IN1
data5x[4] => sub_wire1[44].IN1
data5x[5] => sub_wire1[45].IN1
data5x[6] => sub_wire1[46].IN1
data5x[7] => sub_wire1[47].IN1
data6x[0] => sub_wire1[48].IN1
data6x[1] => sub_wire1[49].IN1
data6x[2] => sub_wire1[50].IN1
data6x[3] => sub_wire1[51].IN1
data6x[4] => sub_wire1[52].IN1
data6x[5] => sub_wire1[53].IN1
data6x[6] => sub_wire1[54].IN1
data6x[7] => sub_wire1[55].IN1
sel[0] => sel[0].IN1
sel[1] => sel[1].IN1
sel[2] => sel[2].IN1
result[0] <= lpm_mux:LPM_MUX_component.result
result[1] <= lpm_mux:LPM_MUX_component.result
result[2] <= lpm_mux:LPM_MUX_component.result
result[3] <= lpm_mux:LPM_MUX_component.result
result[4] <= lpm_mux:LPM_MUX_component.result
result[5] <= lpm_mux:LPM_MUX_component.result
result[6] <= lpm_mux:LPM_MUX_component.result
result[7] <= lpm_mux:LPM_MUX_component.result


|mux21a2627|lpm_mux1:inst21|lpm_mux:LPM_MUX_component
data[0][0] => mux_lrc:auto_generated.data[0]
data[0][1] => mux_lrc:auto_generated.data[1]
data[0][2] => mux_lrc:auto_generated.data[2]
data[0][3] => mux_lrc:auto_generated.data[3]
data[0][4] => mux_lrc:auto_generated.data[4]
data[0][5] => mux_lrc:auto_generated.data[5]
data[0][6] => mux_lrc:auto_generated.data[6]
data[0][7] => mux_lrc:auto_generated.data[7]
data[1][0] => mux_lrc:auto_generated.data[8]
data[1][1] => mux_lrc:auto_generated.data[9]
data[1][2] => mux_lrc:auto_generated.data[10]
data[1][3] => mux_lrc:auto_generated.data[11]
data[1][4] => mux_lrc:auto_generated.data[12]
data[1][5] => mux_lrc:auto_generated.data[13]
data[1][6] => mux_lrc:auto_generated.data[14]
data[1][7] => mux_lrc:auto_generated.data[15]
data[2][0] => mux_lrc:auto_generated.data[16]
data[2][1] => mux_lrc:auto_generated.data[17]
data[2][2] => mux_lrc:auto_generated.data[18]
data[2][3] => mux_lrc:auto_generated.data[19]
data[2][4] => mux_lrc:auto_generated.data[20]
data[2][5] => mux_lrc:auto_generated.data[21]
data[2][6] => mux_lrc:auto_generated.data[22]
data[2][7] => mux_lrc:auto_generated.data[23]
data[3][0] => mux_lrc:auto_generated.data[24]
data[3][1] => mux_lrc:auto_generated.data[25]
data[3][2] => mux_lrc:auto_generated.data[26]
data[3][3] => mux_lrc:auto_generated.data[27]
data[3][4] => mux_lrc:auto_generated.data[28]
data[3][5] => mux_lrc:auto_generated.data[29]
data[3][6] => mux_lrc:auto_generated.data[30]
data[3][7] => mux_lrc:auto_generated.data[31]
data[4][0] => mux_lrc:auto_generated.data[32]
data[4][1] => mux_lrc:auto_generated.data[33]
data[4][2] => mux_lrc:auto_generated.data[34]
data[4][3] => mux_lrc:auto_generated.data[35]
data[4][4] => mux_lrc:auto_generated.data[36]
data[4][5] => mux_lrc:auto_generated.data[37]
data[4][6] => mux_lrc:auto_generated.data[38]
data[4][7] => mux_lrc:auto_generated.data[39]
data[5][0] => mux_lrc:auto_generated.data[40]
data[5][1] => mux_lrc:auto_generated.data[41]
data[5][2] => mux_lrc:auto_generated.data[42]
data[5][3] => mux_lrc:auto_generated.data[43]
data[5][4] => mux_lrc:auto_generated.data[44]
data[5][5] => mux_lrc:auto_generated.data[45]
data[5][6] => mux_lrc:auto_generated.data[46]
data[5][7] => mux_lrc:auto_generated.data[47]
data[6][0] => mux_lrc:auto_generated.data[48]
data[6][1] => mux_lrc:auto_generated.data[49]
data[6][2] => mux_lrc:auto_generated.data[50]
data[6][3] => mux_lrc:auto_generated.data[51]
data[6][4] => mux_lrc:auto_generated.data[52]
data[6][5] => mux_lrc:auto_generated.data[53]
data[6][6] => mux_lrc:auto_generated.data[54]
data[6][7] => mux_lrc:auto_generated.data[55]
sel[0] => mux_lrc:auto_generated.sel[0]
sel[1] => mux_lrc:auto_generated.sel[1]
sel[2] => mux_lrc:auto_generated.sel[2]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_lrc:auto_generated.result[0]
result[1] <= mux_lrc:auto_generated.result[1]
result[2] <= mux_lrc:auto_generated.result[2]
result[3] <= mux_lrc:auto_generated.result[3]
result[4] <= mux_lrc:auto_generated.result[4]
result[5] <= mux_lrc:auto_generated.result[5]
result[6] <= mux_lrc:auto_generated.result[6]
result[7] <= mux_lrc:auto_generated.result[7]


|mux21a2627|lpm_mux1:inst21|lpm_mux:LPM_MUX_component|mux_lrc:auto_generated
data[0] => _.IN0
data[0] => _.IN0
data[1] => _.IN0
data[1] => _.IN0
data[2] => _.IN0
data[2] => _.IN0
data[3] => _.IN0
data[3] => _.IN0
data[4] => _.IN0
data[4] => _.IN0
data[5] => _.IN0
data[5] => _.IN0
data[6] => _.IN0
data[6] => _.IN0
data[7] => _.IN0
data[7] => _.IN0
data[8] => _.IN0
data[9] => _.IN0
data[10] => _.IN0
data[11] => _.IN0
data[12] => _.IN0
data[13] => _.IN0
data[14] => _.IN0
data[15] => _.IN0
data[16] => _.IN1
data[16] => _.IN1
data[17] => _.IN1
data[17] => _.IN1
data[18] => _.IN1
data[18] => _.IN1
data[19] => _.IN1
data[19] => _.IN1
data[20] => _.IN1
data[20] => _.IN1
data[21] => _.IN1
data[21] => _.IN1
data[22] => _.IN1
data[22] => _.IN1
data[23] => _.IN1
data[23] => _.IN1
data[24] => _.IN0
data[25] => _.IN0
data[26] => _.IN0
data[27] => _.IN0
data[28] => _.IN0
data[29] => _.IN0
data[30] => _.IN0
data[31] => _.IN0
data[32] => _.IN0
data[32] => _.IN0
data[33] => _.IN0
data[33] => _.IN0
data[34] => _.IN0
data[34] => _.IN0
data[35] => _.IN0
data[35] => _.IN0
data[36] => _.IN0
data[36] => _.IN0
data[37] => _.IN0
data[37] => _.IN0
data[38] => _.IN0
data[38] => _.IN0
data[39] => _.IN0
data[39] => _.IN0
data[40] => _.IN0
data[41] => _.IN0
data[42] => _.IN0
data[43] => _.IN0
data[44] => _.IN0
data[45] => _.IN0
data[46] => _.IN0
data[47] => _.IN0
data[48] => _.IN1
data[48] => _.IN1
data[49] => _.IN1
data[49] => _.IN1
data[50] => _.IN1
data[50] => _.IN1
data[51] => _.IN1
data[51] => _.IN1
data[52] => _.IN1
data[52] => _.IN1
data[53] => _.IN1
data[53] => _.IN1
data[54] => _.IN1
data[54] => _.IN1
data[55] => _.IN1
data[55] => _.IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[2] => result_node[7].IN0
sel[2] => _.IN0
sel[2] => result_node[6].IN0
sel[2] => _.IN0
sel[2] => result_node[5].IN0
sel[2] => _.IN0
sel[2] => result_node[4].IN0
sel[2] => _.IN0
sel[2] => result_node[3].IN0
sel[2] => _.IN0
sel[2] => result_node[2].IN0
sel[2] => _.IN0
sel[2] => result_node[1].IN0
sel[2] => _.IN0
sel[2] => result_node[0].IN0
sel[2] => _.IN0


|mux21a2627|LPM_RAM_DQ:_RAM_BUSIN2
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]


|mux21a2627|LPM_RAM_DQ:_RAM_BUSIN2|altram:sram
we => _.IN0
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
data[6] => altsyncram:ram_block.data_a[6]
data[7] => altsyncram:ram_block.data_a[7]
address[0] => altsyncram:ram_block.address_a[0]
address[1] => altsyncram:ram_block.address_a[1]
address[2] => altsyncram:ram_block.address_a[2]
address[3] => altsyncram:ram_block.address_a[3]
address[4] => altsyncram:ram_block.address_a[4]
address[5] => altsyncram:ram_block.address_a[5]
address[6] => altsyncram:ram_block.address_a[6]
address[7] => altsyncram:ram_block.address_a[7]
clocki => altsyncram:ram_block.clock0
clocko => ~NO_FANOUT~
be => _.IN1
q[0] <= altsyncram:ram_block.q_a[0]
q[1] <= altsyncram:ram_block.q_a[1]
q[2] <= altsyncram:ram_block.q_a[2]
q[3] <= altsyncram:ram_block.q_a[3]
q[4] <= altsyncram:ram_block.q_a[4]
q[5] <= altsyncram:ram_block.q_a[5]
q[6] <= altsyncram:ram_block.q_a[6]
q[7] <= altsyncram:ram_block.q_a[7]


|mux21a2627|LPM_RAM_DQ:_RAM_BUSIN2|altram:sram|altsyncram:ram_block
wren_a => altsyncram_ap71:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_ap71:auto_generated.data_a[0]
data_a[1] => altsyncram_ap71:auto_generated.data_a[1]
data_a[2] => altsyncram_ap71:auto_generated.data_a[2]
data_a[3] => altsyncram_ap71:auto_generated.data_a[3]
data_a[4] => altsyncram_ap71:auto_generated.data_a[4]
data_a[5] => altsyncram_ap71:auto_generated.data_a[5]
data_a[6] => altsyncram_ap71:auto_generated.data_a[6]
data_a[7] => altsyncram_ap71:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ap71:auto_generated.address_a[0]
address_a[1] => altsyncram_ap71:auto_generated.address_a[1]
address_a[2] => altsyncram_ap71:auto_generated.address_a[2]
address_a[3] => altsyncram_ap71:auto_generated.address_a[3]
address_a[4] => altsyncram_ap71:auto_generated.address_a[4]
address_a[5] => altsyncram_ap71:auto_generated.address_a[5]
address_a[6] => altsyncram_ap71:auto_generated.address_a[6]
address_a[7] => altsyncram_ap71:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ap71:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ap71:auto_generated.q_a[0]
q_a[1] <= altsyncram_ap71:auto_generated.q_a[1]
q_a[2] <= altsyncram_ap71:auto_generated.q_a[2]
q_a[3] <= altsyncram_ap71:auto_generated.q_a[3]
q_a[4] <= altsyncram_ap71:auto_generated.q_a[4]
q_a[5] <= altsyncram_ap71:auto_generated.q_a[5]
q_a[6] <= altsyncram_ap71:auto_generated.q_a[6]
q_a[7] <= altsyncram_ap71:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|mux21a2627|LPM_RAM_DQ:_RAM_BUSIN2|altram:sram|altsyncram:ram_block|altsyncram_ap71:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE


|mux21a2627|Reg8:_AR_BUSIN3
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~


|mux21a2627|BUSMUX:inst28
dataa[0] => lpm_mux:$00000.data[0][0]
dataa[1] => lpm_mux:$00000.data[0][1]
dataa[2] => lpm_mux:$00000.data[0][2]
dataa[3] => lpm_mux:$00000.data[0][3]
dataa[4] => lpm_mux:$00000.data[0][4]
dataa[5] => lpm_mux:$00000.data[0][5]
dataa[6] => lpm_mux:$00000.data[0][6]
dataa[7] => lpm_mux:$00000.data[0][7]
datab[0] => lpm_mux:$00000.data[1][0]
datab[1] => lpm_mux:$00000.data[1][1]
datab[2] => lpm_mux:$00000.data[1][2]
datab[3] => lpm_mux:$00000.data[1][3]
datab[4] => lpm_mux:$00000.data[1][4]
datab[5] => lpm_mux:$00000.data[1][5]
datab[6] => lpm_mux:$00000.data[1][6]
datab[7] => lpm_mux:$00000.data[1][7]
sel => lpm_mux:$00000.sel[0]
result[0] <= lpm_mux:$00000.result[0]
result[1] <= lpm_mux:$00000.result[1]
result[2] <= lpm_mux:$00000.result[2]
result[3] <= lpm_mux:$00000.result[3]
result[4] <= lpm_mux:$00000.result[4]
result[5] <= lpm_mux:$00000.result[5]
result[6] <= lpm_mux:$00000.result[6]
result[7] <= lpm_mux:$00000.result[7]


|mux21a2627|BUSMUX:inst28|lpm_mux:$00000
data[0][0] => mux_erc:auto_generated.data[0]
data[0][1] => mux_erc:auto_generated.data[1]
data[0][2] => mux_erc:auto_generated.data[2]
data[0][3] => mux_erc:auto_generated.data[3]
data[0][4] => mux_erc:auto_generated.data[4]
data[0][5] => mux_erc:auto_generated.data[5]
data[0][6] => mux_erc:auto_generated.data[6]
data[0][7] => mux_erc:auto_generated.data[7]
data[1][0] => mux_erc:auto_generated.data[8]
data[1][1] => mux_erc:auto_generated.data[9]
data[1][2] => mux_erc:auto_generated.data[10]
data[1][3] => mux_erc:auto_generated.data[11]
data[1][4] => mux_erc:auto_generated.data[12]
data[1][5] => mux_erc:auto_generated.data[13]
data[1][6] => mux_erc:auto_generated.data[14]
data[1][7] => mux_erc:auto_generated.data[15]
sel[0] => mux_erc:auto_generated.sel[0]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_erc:auto_generated.result[0]
result[1] <= mux_erc:auto_generated.result[1]
result[2] <= mux_erc:auto_generated.result[2]
result[3] <= mux_erc:auto_generated.result[3]
result[4] <= mux_erc:auto_generated.result[4]
result[5] <= mux_erc:auto_generated.result[5]
result[6] <= mux_erc:auto_generated.result[6]
result[7] <= mux_erc:auto_generated.result[7]


|mux21a2627|BUSMUX:inst28|lpm_mux:$00000|mux_erc:auto_generated
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0


|mux21a2627|lpm_counter0:_PC
aclr => aclr.IN1
aload => aload.IN1
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
q[0] <= lpm_counter:LPM_COUNTER_component.q
q[1] <= lpm_counter:LPM_COUNTER_component.q
q[2] <= lpm_counter:LPM_COUNTER_component.q
q[3] <= lpm_counter:LPM_COUNTER_component.q
q[4] <= lpm_counter:LPM_COUNTER_component.q
q[5] <= lpm_counter:LPM_COUNTER_component.q
q[6] <= lpm_counter:LPM_COUNTER_component.q
q[7] <= lpm_counter:LPM_COUNTER_component.q


|mux21a2627|lpm_counter0:_PC|lpm_counter:LPM_COUNTER_component
clock => cntr_b6j:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => cntr_b6j:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => cntr_b6j:auto_generated.aload
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => cntr_b6j:auto_generated.data[0]
data[1] => cntr_b6j:auto_generated.data[1]
data[2] => cntr_b6j:auto_generated.data[2]
data[3] => cntr_b6j:auto_generated.data[3]
data[4] => cntr_b6j:auto_generated.data[4]
data[5] => cntr_b6j:auto_generated.data[5]
data[6] => cntr_b6j:auto_generated.data[6]
data[7] => cntr_b6j:auto_generated.data[7]
cin => ~NO_FANOUT~
q[0] <= cntr_b6j:auto_generated.q[0]
q[1] <= cntr_b6j:auto_generated.q[1]
q[2] <= cntr_b6j:auto_generated.q[2]
q[3] <= cntr_b6j:auto_generated.q[3]
q[4] <= cntr_b6j:auto_generated.q[4]
q[5] <= cntr_b6j:auto_generated.q[5]
q[6] <= cntr_b6j:auto_generated.q[6]
q[7] <= cntr_b6j:auto_generated.q[7]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|mux21a2627|lpm_counter0:_PC|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated
aclr => aclr_actual.IN0
aclr => latch_signal[7].IN0
aclr => latch_signal[6].IN0
aclr => latch_signal[5].IN0
aclr => latch_signal[4].IN0
aclr => latch_signal[3].IN0
aclr => latch_signal[2].IN0
aclr => latch_signal[1].IN0
aclr => latch_signal[0].IN0
aclr => safe_q[7].IN0
aload => mux211_dataout.IN0
aload => _.IN0
aload => mux2111_dataout.IN0
aload => _.IN0
aload => mux2113_dataout.IN0
aload => _.IN0
aload => mux2115_dataout.IN0
aload => _.IN0
aload => mux213_dataout.IN0
aload => _.IN0
aload => mux215_dataout.IN0
aload => _.IN0
aload => mux217_dataout.IN0
aload => _.IN0
aload => mux219_dataout.IN0
aload => _.IN0
aload => aclr_actual.IN1
aload => _.IN0
aload => _.IN0
aload => _.IN0
aload => _.IN0
aload => _.IN0
aload => _.IN0
aload => _.IN0
aload => _.IN0
aload => _.IN0
clock => counter_reg_bit[7].CLK
clock => counter_reg_bit[6].CLK
clock => counter_reg_bit[5].CLK
clock => counter_reg_bit[4].CLK
clock => counter_reg_bit[3].CLK
clock => counter_reg_bit[2].CLK
clock => counter_reg_bit[1].CLK
clock => counter_reg_bit[0].CLK
data[0] => _.IN1
data[0] => _.IN0
data[0] => _.IN1
data[1] => _.IN1
data[1] => _.IN0
data[1] => _.IN1
data[2] => _.IN1
data[2] => _.IN0
data[2] => _.IN1
data[3] => _.IN1
data[3] => _.IN0
data[3] => _.IN1
data[4] => _.IN1
data[4] => _.IN0
data[4] => _.IN1
data[5] => _.IN1
data[5] => _.IN0
data[5] => _.IN1
data[6] => _.IN1
data[6] => _.IN0
data[6] => _.IN1
data[7] => _.IN1
data[7] => _.IN0
data[7] => _.IN1
q[0] <= safe_q[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= safe_q[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= safe_q[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= safe_q[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= safe_q[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= safe_q[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= safe_q[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= safe_q[7].DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|decodec:inst7
LDPC <= inst13.DB_MAX_OUTPUT_PORT_TYPE
A => inst14.IN0
A => inst.IN0
A => inst10.IN0
B => inst13.IN1
B => inst15.IN0
B => inst9.IN1
B => inst10.IN1
C => inst13.IN2
C => inst16.IN0
C => inst11.IN2
P[1] <= inst.DB_MAX_OUTPUT_PORT_TYPE
P[2] <= inst9.DB_MAX_OUTPUT_PORT_TYPE
P[3] <= inst10.DB_MAX_OUTPUT_PORT_TYPE
P[4] <= inst11.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|Registers_3:_R4-5-6_BUSIN4-5-6
R0[0] <= Reg8:inst1.Q[0]
R0[1] <= Reg8:inst1.Q[1]
R0[2] <= Reg8:inst1.Q[2]
R0[3] <= Reg8:inst1.Q[3]
R0[4] <= Reg8:inst1.Q[4]
R0[5] <= Reg8:inst1.Q[5]
R0[6] <= Reg8:inst1.Q[6]
R0[7] <= Reg8:inst1.Q[7]
T4 => inst7.IN0
T4 => inst6.IN0
T4 => inst.IN0
LDR0 => inst2.IN0
D[0] => Reg8:inst1.D[0]
D[0] => Reg8:inst5.D[0]
D[0] => Reg8:inst8.D[0]
D[1] => Reg8:inst1.D[1]
D[1] => Reg8:inst5.D[1]
D[1] => Reg8:inst8.D[1]
D[2] => Reg8:inst1.D[2]
D[2] => Reg8:inst5.D[2]
D[2] => Reg8:inst8.D[2]
D[3] => Reg8:inst1.D[3]
D[3] => Reg8:inst5.D[3]
D[3] => Reg8:inst8.D[3]
D[4] => Reg8:inst1.D[4]
D[4] => Reg8:inst5.D[4]
D[4] => Reg8:inst8.D[4]
D[5] => Reg8:inst1.D[5]
D[5] => Reg8:inst5.D[5]
D[5] => Reg8:inst8.D[5]
D[6] => Reg8:inst1.D[6]
D[6] => Reg8:inst5.D[6]
D[6] => Reg8:inst8.D[6]
D[7] => Reg8:inst1.D[7]
D[7] => Reg8:inst5.D[7]
D[7] => Reg8:inst8.D[7]
R1[0] <= Reg8:inst5.Q[0]
R1[1] <= Reg8:inst5.Q[1]
R1[2] <= Reg8:inst5.Q[2]
R1[3] <= Reg8:inst5.Q[3]
R1[4] <= Reg8:inst5.Q[4]
R1[5] <= Reg8:inst5.Q[5]
R1[6] <= Reg8:inst5.Q[6]
R1[7] <= Reg8:inst5.Q[7]
LDR1 => inst3.IN0
R2[0] <= Reg8:inst8.Q[0]
R2[1] <= Reg8:inst8.Q[1]
R2[2] <= Reg8:inst8.Q[2]
R2[3] <= Reg8:inst8.Q[3]
R2[4] <= Reg8:inst8.Q[4]
R2[5] <= Reg8:inst8.Q[5]
R2[6] <= Reg8:inst8.Q[6]
R2[7] <= Reg8:inst8.Q[7]
LDR2 => inst4.IN0


|mux21a2627|Registers_3:_R4-5-6_BUSIN4-5-6|Reg8:inst1
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~


|mux21a2627|Registers_3:_R4-5-6_BUSIN4-5-6|Reg8:inst5
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~


|mux21a2627|Registers_3:_R4-5-6_BUSIN4-5-6|Reg8:inst8
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~


|mux21a2627|RegControl:inst12
LDR0 <= inst9.DB_MAX_OUTPUT_PORT_TYPE
LDRI => inst9.IN0
LDRI => inst10.IN0
LDRI => inst11.IN0
I3 => inst3.IN0
I2 => inst5.IN0
I1 => inst6.IN0
I1 => inst13.IN2
I0 => inst4.IN0
I0 => inst12.IN3
LDR1 <= inst10.DB_MAX_OUTPUT_PORT_TYPE
LDR2 <= inst11.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|Reg8:_IR
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~


|mux21a2627|74148:inst4
EON <= 83.DB_MAX_OUTPUT_PORT_TYPE
1N => 83.IN0
1N => 103.IN0
2N => 83.IN1
2N => 55.IN0
3N => 83.IN2
3N => 57.IN0
0N => 83.IN3
4N => 83.IN4
4N => 62.IN0
5N => 83.IN5
5N => 106.IN0
6N => 83.IN6
6N => 104.IN0
7N => 107.IN0
7N => 105.IN0
EIN => 65.IN0
GSN <= 84.DB_MAX_OUTPUT_PORT_TYPE
A0N <= 8.DB_MAX_OUTPUT_PORT_TYPE
A1N <= 109.DB_MAX_OUTPUT_PORT_TYPE
A2N <= 9.DB_MAX_OUTPUT_PORT_TYPE


|mux21a2627|decode2_4:inst34
Y[0] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= inst4.DB_MAX_OUTPUT_PORT_TYPE
D[0] => inst.IN1
D[0] => inst10.IN0
D[0] => inst7.IN1
D[1] => inst.IN0
D[1] => inst6.IN0
D[1] => inst9.IN0


|mux21a2627|Reg8:_R2
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~


|mux21a2627|Reg8:_LED_OUT
Q[0] <= 19.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= 18.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= 17.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= 16.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= 15.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= 14.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= 13.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= <GND>
CLK => 13.CLK
CLK => 14.CLK
CLK => 15.CLK
CLK => 16.CLK
CLK => 17.CLK
CLK => 18.CLK
CLK => 19.CLK
D[0] => 19.DATAIN
D[1] => 18.DATAIN
D[2] => 17.DATAIN
D[3] => 16.DATAIN
D[4] => 15.DATAIN
D[5] => 14.DATAIN
D[6] => 13.DATAIN
D[7] => ~NO_FANOUT~