{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1698129349533 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1698129349533 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "PC_AR2627 EP4CE55F23C8 " "Selected device EP4CE55F23C8 for design \"PC_AR2627\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1698129349538 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1698129349580 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1698129349580 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1698129349734 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1698129349737 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F23C8 " "Device EP4CE15F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129349841 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F23C8 " "Device EP4CE40F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129349841 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F23C8 " "Device EP4CE30F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129349841 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F23C8 " "Device EP4CE75F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129349841 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F23C8 " "Device EP4CE115F23C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1698129349841 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1698129349841 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 153 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129349843 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 155 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129349843 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 157 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129349843 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 159 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129349843 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/17.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 161 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1698129349843 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1698129349843 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1698129349844 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "21 21 " "No exact pin location assignment(s) for 21 pins of 21 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1698129350191 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "8 " "TimeQuest Timing Analyzer is analyzing 8 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1698129350319 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PC_AR2627.sdc " "Synopsys Design Constraints File file not found: 'PC_AR2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1698129350320 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1698129350320 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1698129350321 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1698129350322 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1698129350322 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "LOAD~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node LOAD~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~14 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~14" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 94 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated\|aclr_actual~0 " "Destination node lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated\|aclr_actual~0" {  } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/cntr_b6j.tdf" 94 2 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 95 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[6\]~16 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[6\]~16" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 97 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[5\]~18 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[5\]~18" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[4\]~20 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[4\]~20" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 101 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[3\]~22 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[3\]~22" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 103 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[2\]~24 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[2\]~24" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 105 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[1\]~26 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[1\]~26" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 107 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[0\]~28 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[0\]~28" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 109 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~30 " "Destination node busmux:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\|result_node\[7\]~30" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 29 13 0 } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 127 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1698129350349 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1698129350349 ""}  } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 328 152 320 344 "LOAD" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 138 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1698129350349 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "T2~input (placed in PIN T2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node T2~input (placed in PIN T2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1698129350349 ""}  } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 192 152 320 208 "T2" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 148 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1698129350349 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "T4~input (placed in PIN T1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node T4~input (placed in PIN T1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1698129350349 ""}  } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 400 152 320 416 "T4" "" } } } } { "temporary_test_loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 0 { 0 ""} 0 140 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1698129350349 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1698129350500 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1698129350500 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1698129350500 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1698129350501 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1698129350501 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1698129350501 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1698129350501 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1698129350501 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1698129350509 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1698129350509 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1698129350509 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "18 unused 2.5V 10 8 0 " "Number of I/O pins in group: 18 (unused VREF, 2.5V VCCIO, 10 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1698129350510 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1698129350510 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1698129350510 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 28 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 39 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  39 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 42 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 43 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 41 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 38 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  38 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 43 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1698129350511 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1698129350511 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1698129350511 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129350527 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1698129350530 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1698129351702 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129351762 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1698129351778 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1698129353773 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129353773 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1698129353917 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y20 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y20" {  } { { "loc" "" { Generic "D:/Projects/quartus/pc_ar/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y20"} { { 12 { 0 ""} 0 10 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1698129355001 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1698129355001 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1698129355294 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1698129355294 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129355297 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.12 " "Total time spent on timing analysis during the Fitter is 0.12 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1698129355385 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1698129355391 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1698129355519 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1698129355519 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1698129355646 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1698129355909 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Projects/quartus/pc_ar/output_files/PC_AR2627.fit.smsg " "Generated suppressed messages file D:/Projects/quartus/pc_ar/output_files/PC_AR2627.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1698129356151 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6560 " "Peak virtual memory: 6560 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698129356389 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 14:35:56 2023 " "Processing ended: Tue Oct 24 14:35:56 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698129356389 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698129356389 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698129356389 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1698129356389 ""}