{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1698129338269 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1698129338277 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 24 14:35:38 2023 " "Processing started: Tue Oct 24 14:35:38 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1698129338277 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129338277 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PC_AR2627 -c PC_AR2627 " "Command: quartus_map --read_settings_files=on --write_settings_files=off PC_AR2627 -c PC_AR2627" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129338277 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1698129338623 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1698129338623 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_counter0.v 1 1 " "Found 1 design units, including 1 entities, in source file lpm_counter0.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Found entity 1: lpm_counter0" {  } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129347194 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129347194 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pc_ar2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file pc_ar2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PC_AR2627 " "Found entity 1: PC_AR2627" {  } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129347196 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129347196 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "PC_AR2627 " "Elaborating entity \"PC_AR2627\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1698129347232 ""}
{ "Warning" "WSGN_SEARCH_FILE" "reg8.bdf 1 1 " "Using design file reg8.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Reg8 " "Found entity 1: Reg8" {  } { { "reg8.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/reg8.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129347246 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1698129347246 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reg8 Reg8:inst " "Elaborating entity \"Reg8\" for hierarchy \"Reg8:inst\"" {  } { { "PC_AR2627.bdf" "inst" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 224 856 992 320 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347246 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BUSMUX BUSMUX:inst2 " "Elaborating entity \"BUSMUX\" for hierarchy \"BUSMUX:inst2\"" {  } { { "PC_AR2627.bdf" "inst2" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347264 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "BUSMUX:inst2 " "Elaborated megafunction instantiation \"BUSMUX:inst2\"" {  } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347265 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "BUSMUX:inst2 " "Instantiated megafunction \"BUSMUX:inst2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 8 " "Parameter \"WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129347265 ""}  } { { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1698129347265 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux BUSMUX:inst2\|lpm_mux:\$00000 " "Elaborating entity \"lpm_mux\" for hierarchy \"BUSMUX:inst2\|lpm_mux:\$00000\"" {  } { { "busmux.tdf" "\$00000" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/busmux.tdf" 43 13 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347289 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "BUSMUX:inst2\|lpm_mux:\$00000 BUSMUX:inst2 " "Elaborated megafunction instantiation \"BUSMUX:inst2\|lpm_mux:\$00000\", which is child of megafunction instantiation \"BUSMUX:inst2\"" {  } { { "busmux.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/busmux.tdf" 43 13 0 } } { "PC_AR2627.bdf" "" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 208 648 760 296 "inst2" "" } } } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347290 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_erc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_erc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_erc " "Found entity 1: mux_erc" {  } { { "db/mux_erc.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/mux_erc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129347330 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129347330 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_erc BUSMUX:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated " "Elaborating entity \"mux_erc\" for hierarchy \"BUSMUX:inst2\|lpm_mux:\$00000\|mux_erc:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347330 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst5 " "Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst5\"" {  } { { "PC_AR2627.bdf" "inst5" { Schematic "D:/Projects/quartus/pc_ar/PC_AR2627.bdf" { { 136 408 552 232 "inst5" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347338 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component " "Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\"" {  } { { "lpm_counter0.v" "LPM_COUNTER_component" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 70 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347371 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component " "Elaborated megafunction instantiation \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\"" {  } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 70 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347372 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component " "Instantiated megafunction \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129347372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_port_updown PORT_UNUSED " "Parameter \"lpm_port_updown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129347372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129347372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1698129347372 ""}  } { { "lpm_counter0.v" "" { Text "D:/Projects/quartus/pc_ar/lpm_counter0.v" 70 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1698129347372 ""}
{ "Warning" "WTDFX_ASSERTION" "Counter will power up to an undefined state.  An asynchronous signal should be asserted before the counter reaches a known state. " "Assertion warning: Counter will power up to an undefined state.  An asynchronous signal should be asserted before the counter reaches a known state." {  } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/cntr_b6j.tdf" 152 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129347412 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_b6j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_b6j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_b6j " "Found entity 1: cntr_b6j" {  } { { "db/cntr_b6j.tdf" "" { Text "D:/Projects/quartus/pc_ar/db/cntr_b6j.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1698129347413 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129347413 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_b6j lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated " "Elaborating entity \"cntr_b6j\" for hierarchy \"lpm_counter0:inst5\|lpm_counter:LPM_COUNTER_component\|cntr_b6j:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_counter.tdf" 258 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129347413 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1698129347802 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1698129348178 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1698129348178 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1698129348207 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1698129348207 ""} { "Info" "ICUT_CUT_TM_LCELLS" "50 " "Implemented 50 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1698129348207 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1698129348207 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4840 " "Peak virtual memory: 4840 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1698129348217 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 24 14:35:48 2023 " "Processing ended: Tue Oct 24 14:35:48 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1698129348217 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1698129348217 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1698129348217 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1698129348217 ""}