TimeQuest Timing Analyzer report for PC_AR2627 Tue Oct 24 14:36:01 2023 Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. Clocks 5. Slow 1200mV 85C Model Fmax Summary 6. Timing Closure Recommendations 7. Slow 1200mV 85C Model Setup Summary 8. Slow 1200mV 85C Model Hold Summary 9. Slow 1200mV 85C Model Recovery Summary 10. Slow 1200mV 85C Model Removal Summary 11. Slow 1200mV 85C Model Minimum Pulse Width Summary 12. Slow 1200mV 85C Model Setup: 'T2' 13. Slow 1200mV 85C Model Setup: 'T4' 14. Slow 1200mV 85C Model Hold: 'T4' 15. Slow 1200mV 85C Model Hold: 'T2' 16. Slow 1200mV 85C Model Recovery: 'T2' 17. Slow 1200mV 85C Model Removal: 'T2' 18. Slow 1200mV 85C Model Metastability Summary 19. Slow 1200mV 0C Model Fmax Summary 20. Slow 1200mV 0C Model Setup Summary 21. Slow 1200mV 0C Model Hold Summary 22. Slow 1200mV 0C Model Recovery Summary 23. Slow 1200mV 0C Model Removal Summary 24. Slow 1200mV 0C Model Minimum Pulse Width Summary 25. Slow 1200mV 0C Model Setup: 'T2' 26. Slow 1200mV 0C Model Setup: 'T4' 27. Slow 1200mV 0C Model Hold: 'T4' 28. Slow 1200mV 0C Model Hold: 'T2' 29. Slow 1200mV 0C Model Recovery: 'T2' 30. Slow 1200mV 0C Model Removal: 'T2' 31. Slow 1200mV 0C Model Metastability Summary 32. Fast 1200mV 0C Model Setup Summary 33. Fast 1200mV 0C Model Hold Summary 34. Fast 1200mV 0C Model Recovery Summary 35. Fast 1200mV 0C Model Removal Summary 36. Fast 1200mV 0C Model Minimum Pulse Width Summary 37. Fast 1200mV 0C Model Setup: 'T2' 38. Fast 1200mV 0C Model Setup: 'T4' 39. Fast 1200mV 0C Model Hold: 'T4' 40. Fast 1200mV 0C Model Hold: 'T2' 41. Fast 1200mV 0C Model Recovery: 'T2' 42. Fast 1200mV 0C Model Removal: 'T2' 43. Fast 1200mV 0C Model Metastability Summary 44. Multicorner Timing Analysis Summary 45. Board Trace Model Assignments 46. Input Transition Times 47. Signal Integrity Metrics (Slow 1200mv 0c Model) 48. Signal Integrity Metrics (Slow 1200mv 85c Model) 49. Signal Integrity Metrics (Fast 1200mv 0c Model) 50. Setup Transfers 51. Hold Transfers 52. Recovery Transfers 53. Removal Transfers 54. Report TCCS 55. Report RSKM 56. Unconstrained Paths Summary 57. Clock Status Summary 58. Unconstrained Input Ports 59. Unconstrained Output Ports 60. Unconstrained Input Ports 61. Unconstrained Output Ports 62. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2017 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +-----------------------+-----------------------------------------------------+ ; Quartus Prime Version ; Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition ; ; Timing Analyzer ; TimeQuest ; ; Revision Name ; PC_AR2627 ; ; Device Family ; Cyclone IV E ; ; Device Name ; EP4CE55F23C8 ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +-----------------------+-----------------------------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 16 ; ; Maximum allowed ; 16 ; ; ; ; ; Average used ; 1.07 ; ; Maximum used ; 16 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 0.5% ; ; Processors 3-16 ; 0.5% ; +----------------------------+-------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ ; LOAD ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { LOAD } ; ; T2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { T2 } ; ; T4 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { T4 } ; +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +--------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ ; 232.02 MHz ; 232.02 MHz ; T2 ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. ---------------------------------- ; Timing Closure Recommendations ; ---------------------------------- HTML report is unavailable in plain text report export. +-------------------------------------+ ; Slow 1200mV 85C Model Setup Summary ; +-------+--------+--------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+--------------------+ ; T2 ; -3.359 ; -22.917 ; ; T4 ; -2.795 ; -21.045 ; +-------+--------+--------------------+ +------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +-------+-------+--------------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+--------------------+ ; T4 ; 0.584 ; 0.000 ; ; T2 ; 0.624 ; 0.000 ; +-------+-------+--------------------+ +----------------------------------------+ ; Slow 1200mV 85C Model Recovery Summary ; +-------+--------+-----------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+-----------------------+ ; T2 ; -2.360 ; -18.581 ; +-------+--------+-----------------------+ +---------------------------------------+ ; Slow 1200mV 85C Model Removal Summary ; +-------+-------+-----------------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+-----------------------+ ; T2 ; 1.876 ; 0.000 ; +-------+-------+-----------------------+ +---------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +-------+--------+----------------------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+----------------------------------+ ; T2 ; -3.000 ; -14.896 ; ; T4 ; -3.000 ; -14.896 ; ; LOAD ; -3.000 ; -3.000 ; +-------+--------+----------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'T2' ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -3.359 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.769 ; ; -3.310 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 4.225 ; ; -3.164 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.574 ; ; -3.157 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 4.072 ; ; -3.152 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.045 ; 3.588 ; ; -3.125 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.068 ; 3.538 ; ; -3.115 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.086 ; 4.030 ; ; -3.106 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 4.021 ; ; -3.080 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.995 ; ; -3.053 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.968 ; ; -3.041 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.451 ; ; -2.992 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.907 ; ; -2.972 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.887 ; ; -2.971 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.069 ; 3.383 ; ; -2.962 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.877 ; ; -2.957 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.045 ; 3.393 ; ; -2.930 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.068 ; 3.343 ; ; -2.911 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.826 ; ; -2.890 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.300 ; ; -2.885 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.800 ; ; -2.856 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.266 ; ; -2.853 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.263 ; ; -2.839 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.754 ; ; -2.839 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.754 ; ; -2.834 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.045 ; 3.270 ; ; -2.826 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.068 ; 3.239 ; ; -2.820 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.230 ; ; -2.807 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.722 ; ; -2.798 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.713 ; ; -2.787 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.702 ; ; -2.777 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.692 ; ; -2.776 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.069 ; 3.188 ; ; -2.774 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.068 ; 3.187 ; ; -2.771 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.686 ; ; -2.755 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.670 ; ; -2.746 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.661 ; ; -2.731 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.141 ; ; -2.707 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.622 ; ; -2.707 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.117 ; ; -2.672 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.069 ; 3.084 ; ; -2.658 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.068 ; ; -2.654 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.569 ; ; -2.653 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.069 ; 3.065 ; ; -2.631 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.069 ; 3.043 ; ; -2.620 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.069 ; 3.032 ; ; -2.613 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.045 ; 3.049 ; ; -2.591 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.071 ; 3.001 ; ; -2.574 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.489 ; ; -2.541 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.456 ; ; -2.517 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.046 ; 2.952 ; ; -2.508 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.045 ; 2.944 ; ; -2.469 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.384 ; ; -2.433 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.348 ; ; -2.399 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.314 ; ; -2.356 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.068 ; 2.769 ; ; -2.347 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.262 ; ; -2.344 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.259 ; ; -2.337 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.252 ; ; -2.327 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.242 ; ; -2.314 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.071 ; 2.724 ; ; -2.254 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.067 ; 2.668 ; ; -2.244 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.071 ; 2.654 ; ; -2.241 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.156 ; ; -2.180 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 1.000 ; -0.086 ; 3.095 ; ; -2.073 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.500 ; -0.071 ; 2.483 ; ; -2.056 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.045 ; 2.492 ; ; -2.013 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; -0.069 ; 2.425 ; ; -1.973 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.086 ; 2.888 ; ; -1.750 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.071 ; 2.160 ; ; -1.686 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; T2 ; T2 ; 1.000 ; -0.086 ; 2.601 ; ; -1.515 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.086 ; 2.430 ; ; -1.498 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.046 ; 1.933 ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'T4' ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; -2.795 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.294 ; ; -2.630 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.129 ; ; -2.628 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.127 ; ; -2.626 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.125 ; ; -2.604 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.103 ; ; -2.593 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.092 ; ; -2.590 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.089 ; ; -2.579 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 0.500 ; 3.018 ; 6.078 ; ; -2.125 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 1.000 ; 3.018 ; 6.124 ; ; -1.969 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 1.000 ; 3.018 ; 5.968 ; ; -1.947 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 1.000 ; 3.018 ; 5.946 ; ; -1.946 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 1.000 ; 3.018 ; 5.945 ; ; -1.932 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 1.000 ; 3.018 ; 5.931 ; ; -1.915 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 1.000 ; 3.018 ; 5.914 ; ; -1.893 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 1.000 ; 3.018 ; 5.892 ; ; -1.824 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 1.000 ; 3.018 ; 5.823 ; ; -0.937 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; Reg8:inst|19 ; LOAD ; T4 ; 0.500 ; -0.070 ; 1.348 ; ; -0.657 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; Reg8:inst|18 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.523 ; ; -0.654 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; Reg8:inst|12 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.520 ; ; -0.631 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; Reg8:inst|13 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.497 ; ; -0.616 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; Reg8:inst|17 ; LOAD ; T4 ; 0.500 ; -0.044 ; 1.053 ; ; -0.606 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; Reg8:inst|16 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.472 ; ; -0.606 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; Reg8:inst|19 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.472 ; ; -0.597 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; Reg8:inst|14 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.463 ; ; -0.567 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; Reg8:inst|17 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.433 ; ; -0.562 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; Reg8:inst|15 ; T2 ; T4 ; 1.000 ; -0.115 ; 1.428 ; ; -0.178 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; Reg8:inst|12 ; LOAD ; T4 ; 0.500 ; -0.066 ; 0.593 ; ; -0.157 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; Reg8:inst|14 ; LOAD ; T4 ; 0.500 ; -0.070 ; 0.568 ; ; -0.157 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; Reg8:inst|15 ; LOAD ; T4 ; 0.500 ; -0.070 ; 0.568 ; ; -0.152 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; Reg8:inst|16 ; LOAD ; T4 ; 0.500 ; -0.067 ; 0.566 ; ; -0.152 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; Reg8:inst|18 ; LOAD ; T4 ; 0.500 ; -0.068 ; 0.565 ; ; -0.127 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; Reg8:inst|13 ; LOAD ; T4 ; 0.500 ; -0.045 ; 0.563 ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'T4' ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; 0.584 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; Reg8:inst|13 ; LOAD ; T4 ; -0.500 ; 0.160 ; 0.496 ; ; 0.598 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; Reg8:inst|15 ; LOAD ; T4 ; -0.500 ; 0.137 ; 0.487 ; ; 0.607 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; Reg8:inst|16 ; LOAD ; T4 ; -0.500 ; 0.139 ; 0.498 ; ; 0.607 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; Reg8:inst|18 ; LOAD ; T4 ; -0.500 ; 0.139 ; 0.498 ; ; 0.610 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; Reg8:inst|14 ; LOAD ; T4 ; -0.500 ; 0.137 ; 0.499 ; ; 0.628 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; Reg8:inst|12 ; LOAD ; T4 ; -0.500 ; 0.140 ; 0.520 ; ; 0.948 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; Reg8:inst|17 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.317 ; ; 0.954 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; Reg8:inst|15 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.323 ; ; 0.978 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; Reg8:inst|14 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.347 ; ; 0.978 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; Reg8:inst|17 ; LOAD ; T4 ; -0.500 ; 0.162 ; 0.892 ; ; 0.986 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; Reg8:inst|16 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.355 ; ; 1.010 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; Reg8:inst|19 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.379 ; ; 1.012 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; Reg8:inst|13 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.381 ; ; 1.027 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; Reg8:inst|12 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.396 ; ; 1.038 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; Reg8:inst|18 ; T2 ; T4 ; 0.000 ; 0.117 ; 1.407 ; ; 1.314 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; Reg8:inst|19 ; LOAD ; T4 ; -0.500 ; 0.137 ; 1.203 ; ; 1.868 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.254 ; ; 1.939 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.325 ; ; 1.942 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.328 ; ; 1.944 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.330 ; ; 1.976 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.362 ; ; 1.977 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.363 ; ; 1.979 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.365 ; ; 2.336 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 0.000 ; 3.134 ; 5.722 ; ; 2.788 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.674 ; ; 2.806 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.692 ; ; 2.819 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.705 ; ; 2.821 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.707 ; ; 2.879 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.765 ; ; 2.881 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.767 ; ; 2.891 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.777 ; ; 2.894 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; -0.500 ; 3.134 ; 5.780 ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'T2' ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 0.624 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; -0.500 ; 0.136 ; 0.512 ; ; 0.854 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.136 ; 0.742 ; ; 0.888 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.139 ; 0.779 ; ; 0.916 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; 0.138 ; 0.806 ; ; 0.958 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.136 ; 0.846 ; ; 0.979 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 0.161 ; 0.892 ; ; 0.991 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.159 ; 0.902 ; ; 1.821 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.119 ; ; 1.900 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.138 ; 1.790 ; ; 2.016 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.314 ; ; 2.151 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.449 ; ; 2.343 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.641 ; ; 2.352 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.240 ; ; 2.404 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.159 ; 2.315 ; ; 2.448 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.746 ; ; 2.462 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.350 ; ; 2.463 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.761 ; ; 2.464 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.762 ; ; 2.485 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.375 ; ; 2.486 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.784 ; ; 2.487 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.785 ; ; 2.506 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.396 ; ; 2.507 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.805 ; ; 2.510 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.808 ; ; 2.527 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.825 ; ; 2.536 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.834 ; ; 2.542 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.161 ; 2.455 ; ; 2.556 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.446 ; ; 2.557 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.855 ; ; 2.559 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.447 ; ; 2.585 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.475 ; ; 2.613 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.161 ; 2.526 ; ; 2.618 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.916 ; ; 2.621 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.919 ; ; 2.627 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.925 ; ; 2.652 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.542 ; ; 2.656 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.546 ; ; 2.664 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.962 ; ; 2.682 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.570 ; ; 2.685 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.983 ; ; 2.692 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.086 ; 2.990 ; ; 2.709 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.161 ; 2.622 ; ; 2.729 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.027 ; ; 2.735 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.033 ; ; 2.743 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.041 ; ; 2.746 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.634 ; ; 2.757 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.645 ; ; 2.763 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.653 ; ; 2.764 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.062 ; ; 2.778 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.666 ; ; 2.820 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.161 ; 2.733 ; ; 2.831 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.129 ; ; 2.832 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.720 ; ; 2.835 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.133 ; ; 2.852 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.740 ; ; 2.856 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.744 ; ; 2.863 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.753 ; ; 2.899 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.197 ; ; 2.916 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.214 ; ; 2.930 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.228 ; ; 2.931 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.229 ; ; 2.942 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.240 ; ; 2.950 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.840 ; ; 2.963 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.136 ; 2.851 ; ; 3.007 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.161 ; 2.920 ; ; 3.021 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.319 ; ; 3.042 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.340 ; ; 3.050 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.138 ; 2.940 ; ; 3.086 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.384 ; ; 3.129 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.427 ; ; 3.150 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.136 ; 3.038 ; ; 3.229 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.086 ; 3.527 ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Recovery: 'T2' ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -2.360 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.858 ; ; -2.360 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.858 ; ; -2.360 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.858 ; ; -2.360 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.858 ; ; -2.338 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.836 ; ; -2.338 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.836 ; ; -2.338 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.836 ; ; -2.127 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; 3.017 ; 5.625 ; ; -1.758 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.756 ; ; -1.758 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.756 ; ; -1.758 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.756 ; ; -1.758 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.756 ; ; -1.727 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.725 ; ; -1.727 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.725 ; ; -1.727 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.725 ; ; -1.459 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 1.000 ; 3.017 ; 5.457 ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Removal: 'T2' ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 1.876 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.261 ; ; 2.133 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.518 ; ; 2.133 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.518 ; ; 2.133 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.518 ; ; 2.163 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.548 ; ; 2.163 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.548 ; ; 2.163 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.548 ; ; 2.163 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.000 ; 3.133 ; 5.548 ; ; 2.535 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.420 ; ; 2.738 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.623 ; ; 2.738 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.623 ; ; 2.738 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.623 ; ; 2.759 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.644 ; ; 2.759 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.644 ; ; 2.759 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.644 ; ; 2.759 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 3.133 ; 5.644 ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ----------------------------------------------- ; Slow 1200mV 85C Model Metastability Summary ; ----------------------------------------------- No synchronizer chains to report. +--------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ ; 249.56 MHz ; 249.56 MHz ; T2 ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +------------------------------------+ ; Slow 1200mV 0C Model Setup Summary ; +-------+--------+-------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+-------------------+ ; T2 ; -3.035 ; -20.735 ; ; T4 ; -2.674 ; -21.011 ; +-------+--------+-------------------+ +-----------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +-------+-------+-------------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+-------------------+ ; T4 ; 0.535 ; 0.000 ; ; T2 ; 0.571 ; 0.000 ; +-------+-------+-------------------+ +---------------------------------------+ ; Slow 1200mV 0C Model Recovery Summary ; +-------+--------+----------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+----------------------+ ; T2 ; -2.230 ; -17.575 ; +-------+--------+----------------------+ +--------------------------------------+ ; Slow 1200mV 0C Model Removal Summary ; +-------+-------+----------------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+----------------------+ ; T2 ; 1.778 ; 0.000 ; +-------+-------+----------------------+ +--------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +-------+--------+---------------------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------------------------+ ; T2 ; -3.000 ; -14.896 ; ; T4 ; -3.000 ; -14.896 ; ; LOAD ; -3.000 ; -3.000 ; +-------+--------+---------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'T2' ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -3.035 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.028 ; 3.489 ; ; -3.007 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.933 ; ; -2.877 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.026 ; 3.333 ; ; -2.863 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.028 ; 3.317 ; ; -2.846 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.772 ; ; -2.837 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.763 ; ; -2.835 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.761 ; ; -2.813 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.006 ; 3.289 ; ; -2.776 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.702 ; ; -2.755 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.028 ; 3.209 ; ; -2.732 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.658 ; ; -2.727 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.653 ; ; -2.713 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.026 ; 3.169 ; ; -2.705 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.026 ; 3.161 ; ; -2.674 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.600 ; ; -2.665 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.591 ; ; -2.663 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.589 ; ; -2.659 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.028 ; 3.113 ; ; -2.641 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.006 ; 3.117 ; ; -2.602 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; -0.028 ; 3.056 ; ; -2.560 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.486 ; ; -2.557 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.483 ; ; -2.552 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.026 ; 3.008 ; ; -2.542 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.998 ; ; -2.541 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.995 ; ; -2.541 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.997 ; ; -2.533 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.006 ; 3.009 ; ; -2.521 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.447 ; ; -2.521 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.447 ; ; -2.516 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.442 ; ; -2.512 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.438 ; ; -2.511 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.437 ; ; -2.506 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.432 ; ; -2.502 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.428 ; ; -2.491 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.417 ; ; -2.481 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.935 ; ; -2.472 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.926 ; ; -2.462 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.916 ; ; -2.451 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.377 ; ; -2.433 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.889 ; ; -2.397 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.853 ; ; -2.388 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.844 ; ; -2.383 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.309 ; ; -2.378 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.834 ; ; -2.369 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.823 ; ; -2.334 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.788 ; ; -2.301 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.006 ; 2.777 ; ; -2.294 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.220 ; ; -2.291 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.006 ; 2.767 ; ; -2.265 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.007 ; 2.740 ; ; -2.230 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.156 ; ; -2.215 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.141 ; ; -2.208 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.134 ; ; -2.201 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.657 ; ; -2.179 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.105 ; ; -2.170 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.096 ; ; -2.143 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.025 ; 2.600 ; ; -2.110 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.036 ; ; -2.101 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.027 ; ; -2.091 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.076 ; 3.017 ; ; -2.091 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.545 ; ; -2.057 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.511 ; ; -2.039 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.076 ; 2.965 ; ; -2.004 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 1.000 ; -0.076 ; 2.930 ; ; -1.880 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; -0.026 ; 2.336 ; ; -1.865 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.319 ; ; -1.824 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.006 ; 2.300 ; ; -1.716 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.076 ; 2.642 ; ; -1.557 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.028 ; 2.011 ; ; -1.493 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; T2 ; T2 ; 1.000 ; -0.076 ; 2.419 ; ; -1.303 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.007 ; 1.778 ; ; -1.293 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.076 ; 2.219 ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'T4' ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; -2.674 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.911 ; ; -2.662 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.899 ; ; -2.660 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.897 ; ; -2.658 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.895 ; ; -2.615 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.852 ; ; -2.614 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.851 ; ; -2.611 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.848 ; ; -2.517 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 0.500 ; 2.755 ; 5.754 ; ; -1.962 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.699 ; ; -1.812 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.549 ; ; -1.792 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.529 ; ; -1.782 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.519 ; ; -1.779 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.516 ; ; -1.762 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.499 ; ; -1.734 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.471 ; ; -1.673 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 1.000 ; 2.755 ; 5.410 ; ; -0.817 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; Reg8:inst|19 ; LOAD ; T4 ; 0.500 ; -0.026 ; 1.273 ; ; -0.566 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; Reg8:inst|18 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.447 ; ; -0.563 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; Reg8:inst|12 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.444 ; ; -0.544 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; Reg8:inst|13 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.425 ; ; -0.544 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; Reg8:inst|17 ; LOAD ; T4 ; 0.500 ; -0.004 ; 1.022 ; ; -0.522 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; Reg8:inst|14 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.403 ; ; -0.511 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; Reg8:inst|16 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.392 ; ; -0.493 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; Reg8:inst|19 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.374 ; ; -0.485 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; Reg8:inst|17 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.366 ; ; -0.484 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; Reg8:inst|15 ; T2 ; T4 ; 1.000 ; -0.101 ; 1.365 ; ; -0.081 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; Reg8:inst|12 ; LOAD ; T4 ; 0.500 ; -0.023 ; 0.540 ; ; -0.063 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; Reg8:inst|14 ; LOAD ; T4 ; 0.500 ; -0.026 ; 0.519 ; ; -0.060 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; Reg8:inst|18 ; LOAD ; T4 ; 0.500 ; -0.024 ; 0.518 ; ; -0.060 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; Reg8:inst|15 ; LOAD ; T4 ; 0.500 ; -0.026 ; 0.516 ; ; -0.059 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; Reg8:inst|16 ; LOAD ; T4 ; 0.500 ; -0.024 ; 0.517 ; ; -0.038 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; Reg8:inst|13 ; LOAD ; T4 ; 0.500 ; -0.005 ; 0.515 ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'T4' ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; 0.535 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; Reg8:inst|13 ; LOAD ; T4 ; -0.500 ; 0.177 ; 0.447 ; ; 0.556 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; Reg8:inst|16 ; LOAD ; T4 ; -0.500 ; 0.158 ; 0.449 ; ; 0.556 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; Reg8:inst|18 ; LOAD ; T4 ; -0.500 ; 0.158 ; 0.449 ; ; 0.560 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; Reg8:inst|14 ; LOAD ; T4 ; -0.500 ; 0.156 ; 0.451 ; ; 0.561 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; Reg8:inst|15 ; LOAD ; T4 ; -0.500 ; 0.156 ; 0.452 ; ; 0.577 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; Reg8:inst|12 ; LOAD ; T4 ; -0.500 ; 0.160 ; 0.472 ; ; 0.845 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; Reg8:inst|17 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.185 ; ; 0.851 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; Reg8:inst|15 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.191 ; ; 0.869 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; Reg8:inst|14 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.209 ; ; 0.874 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; Reg8:inst|17 ; LOAD ; T4 ; -0.500 ; 0.178 ; 0.787 ; ; 0.881 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; Reg8:inst|16 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.221 ; ; 0.900 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; Reg8:inst|13 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.240 ; ; 0.919 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; Reg8:inst|19 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.259 ; ; 0.920 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; Reg8:inst|12 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.260 ; ; 0.928 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; Reg8:inst|18 ; T2 ; T4 ; 0.000 ; 0.105 ; 1.268 ; ; 1.209 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; Reg8:inst|19 ; LOAD ; T4 ; -0.500 ; 0.156 ; 1.100 ; ; 1.658 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 0.000 ; 2.858 ; 4.751 ; ; 1.711 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 0.000 ; 2.858 ; 4.804 ; ; 1.715 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 0.000 ; 2.858 ; 4.808 ; ; 1.716 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 0.000 ; 2.858 ; 4.809 ; ; 1.745 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 0.000 ; 2.858 ; 4.838 ; ; 1.747 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 0.000 ; 2.858 ; 4.840 ; ; 1.749 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 0.000 ; 2.858 ; 4.842 ; ; 2.282 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 0.000 ; 2.858 ; 5.375 ; ; 2.694 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.287 ; ; 2.727 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.320 ; ; 2.754 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.347 ; ; 2.810 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.403 ; ; 2.815 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.408 ; ; 2.820 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.413 ; ; 2.823 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.416 ; ; 2.837 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; -0.500 ; 2.858 ; 5.430 ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'T2' ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 0.571 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; -0.500 ; 0.154 ; 0.460 ; ; 0.797 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.154 ; 0.686 ; ; 0.812 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.158 ; 0.705 ; ; 0.835 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; 0.156 ; 0.726 ; ; 0.869 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.154 ; 0.758 ; ; 0.876 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 0.176 ; 0.787 ; ; 0.883 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.175 ; 0.793 ; ; 1.668 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.076 ; 1.939 ; ; 1.700 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.156 ; 1.591 ; ; 1.817 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.088 ; ; 1.945 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.216 ; ; 2.104 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.375 ; ; 2.148 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.037 ; ; 2.181 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.175 ; 2.091 ; ; 2.203 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.474 ; ; 2.212 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.483 ; ; 2.216 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.107 ; ; 2.219 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.490 ; ; 2.220 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.491 ; ; 2.237 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.126 ; ; 2.240 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.511 ; ; 2.248 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.139 ; ; 2.252 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.523 ; ; 2.259 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.530 ; ; 2.281 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.552 ; ; 2.296 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.185 ; ; 2.297 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.176 ; 2.208 ; ; 2.308 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.199 ; ; 2.312 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.583 ; ; 2.312 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.203 ; ; 2.318 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.589 ; ; 2.349 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.620 ; ; 2.359 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.250 ; ; 2.363 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.634 ; ; 2.389 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.176 ; 2.300 ; ; 2.393 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.664 ; ; 2.400 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.671 ; ; 2.404 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.295 ; ; 2.425 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.696 ; ; 2.432 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.321 ; ; 2.440 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.176 ; 2.351 ; ; 2.441 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.712 ; ; 2.456 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.727 ; ; 2.456 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.347 ; ; 2.457 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.346 ; ; 2.460 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.731 ; ; 2.466 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.737 ; ; 2.474 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.363 ; ; 2.485 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.756 ; ; 2.506 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.395 ; ; 2.536 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.807 ; ; 2.537 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.176 ; 2.448 ; ; 2.546 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.435 ; ; 2.548 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.819 ; ; 2.552 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.443 ; ; 2.566 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.455 ; ; 2.583 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.472 ; ; 2.589 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.860 ; ; 2.599 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.870 ; ; 2.617 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.508 ; ; 2.621 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.892 ; ; 2.627 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.898 ; ; 2.633 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.904 ; ; 2.680 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.569 ; ; 2.696 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.967 ; ; 2.698 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.176 ; 2.609 ; ; 2.709 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 2.980 ; ; 2.713 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.156 ; 2.604 ; ; 2.750 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 3.021 ; ; 2.794 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 3.065 ; ; 2.841 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 0.154 ; 2.730 ; ; 2.857 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.076 ; 3.128 ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Recovery: 'T2' ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -2.230 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.465 ; ; -2.230 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.465 ; ; -2.230 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.465 ; ; -2.230 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.465 ; ; -2.210 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.445 ; ; -2.210 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.445 ; ; -2.210 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.445 ; ; -2.025 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; 2.753 ; 5.260 ; ; -1.617 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.352 ; ; -1.617 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.352 ; ; -1.617 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.352 ; ; -1.617 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.352 ; ; -1.587 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.322 ; ; -1.587 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.322 ; ; -1.587 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.322 ; ; -1.315 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 1.000 ; 2.753 ; 5.050 ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Removal: 'T2' ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 1.778 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.000 ; 2.856 ; 4.869 ; ; 2.039 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.000 ; 2.856 ; 5.130 ; ; 2.039 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.000 ; 2.856 ; 5.130 ; ; 2.039 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.000 ; 2.856 ; 5.130 ; ; 2.068 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.000 ; 2.856 ; 5.159 ; ; 2.068 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.000 ; 2.856 ; 5.159 ; ; 2.068 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.000 ; 2.856 ; 5.159 ; ; 2.068 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.000 ; 2.856 ; 5.159 ; ; 2.481 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.072 ; ; 2.658 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.249 ; ; 2.658 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.249 ; ; 2.658 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.249 ; ; 2.678 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.269 ; ; 2.678 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.269 ; ; 2.678 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.269 ; ; 2.678 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 2.856 ; 5.269 ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ---------------------------------------------- ; Slow 1200mV 0C Model Metastability Summary ; ---------------------------------------------- No synchronizer chains to report. +------------------------------------+ ; Fast 1200mV 0C Model Setup Summary ; +-------+--------+-------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+-------------------+ ; T2 ; -1.551 ; -10.700 ; ; T4 ; -1.172 ; -8.748 ; +-------+--------+-------------------+ +-----------------------------------+ ; Fast 1200mV 0C Model Hold Summary ; +-------+-------+-------------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+-------------------+ ; T4 ; 0.341 ; 0.000 ; ; T2 ; 0.727 ; 0.000 ; +-------+-------+-------------------+ +---------------------------------------+ ; Fast 1200mV 0C Model Recovery Summary ; +-------+--------+----------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+----------------------+ ; T2 ; -1.001 ; -7.868 ; +-------+--------+----------------------+ +--------------------------------------+ ; Fast 1200mV 0C Model Removal Summary ; +-------+-------+----------------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+----------------------+ ; T2 ; 0.768 ; 0.000 ; +-------+-------+----------------------+ +--------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +-------+--------+---------------------------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------------------------+ ; T2 ; -3.000 ; -11.464 ; ; T4 ; -3.000 ; -11.456 ; ; LOAD ; -3.000 ; -3.000 ; +-------+--------+---------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'T2' ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -1.551 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.602 ; ; -1.464 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.403 ; 1.528 ; ; -1.459 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.510 ; ; -1.417 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.469 ; ; -1.407 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.458 ; ; -1.372 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.403 ; 1.436 ; ; -1.366 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.418 ; ; -1.355 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.406 ; ; -1.339 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.390 ; ; -1.325 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.377 ; ; -1.322 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.417 ; 1.372 ; ; -1.320 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.403 ; 1.384 ; ; -1.319 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.370 ; ; -1.317 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.368 ; ; -1.309 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.360 ; ; -1.274 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.326 ; ; -1.270 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.322 ; ; -1.268 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.403 ; 1.332 ; ; -1.247 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.298 ; ; -1.225 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.277 ; ; -1.224 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.276 ; ; -1.222 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.274 ; ; -1.222 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.403 ; 1.286 ; ; -1.187 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.239 ; ; -1.179 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.404 ; 1.242 ; ; -1.179 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.231 ; ; -1.178 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.417 ; 1.228 ; ; -1.143 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.194 ; ; -1.095 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.147 ; ; -1.052 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; -0.417 ; 1.102 ; ; -1.024 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; -0.414 ; 1.077 ; ; -0.983 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.500 ; -0.416 ; 1.034 ; ; -0.983 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; -0.403 ; 1.047 ; ; -0.952 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; -0.415 ; 1.004 ; ; -0.860 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; -0.416 ; 0.911 ; ; -0.850 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.798 ; ; -0.783 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.731 ; ; -0.758 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.706 ; ; -0.753 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.701 ; ; -0.745 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; -0.404 ; 0.808 ; ; -0.736 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.684 ; ; -0.734 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.682 ; ; -0.715 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.663 ; ; -0.706 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.654 ; ; -0.691 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.639 ; ; -0.661 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.609 ; ; -0.654 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.602 ; ; -0.644 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.592 ; ; -0.639 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.587 ; ; -0.623 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.571 ; ; -0.618 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.566 ; ; -0.608 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.556 ; ; -0.580 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.528 ; ; -0.572 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.520 ; ; -0.571 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.519 ; ; -0.566 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.514 ; ; -0.563 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.511 ; ; -0.557 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.505 ; ; -0.520 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.468 ; ; -0.519 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.467 ; ; -0.512 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.460 ; ; -0.483 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.431 ; ; -0.481 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.429 ; ; -0.473 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.421 ; ; -0.464 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.412 ; ; -0.426 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.374 ; ; -0.414 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.362 ; ; -0.371 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.319 ; ; -0.369 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.317 ; ; -0.274 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.222 ; ; -0.158 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.106 ; ; -0.077 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 1.000 ; -0.039 ; 1.025 ; +--------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'T4' ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; -1.172 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 0.500 ; 1.425 ; 3.064 ; ; -1.115 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 0.500 ; 1.425 ; 3.007 ; ; -1.093 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 0.500 ; 1.425 ; 2.985 ; ; -1.088 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 0.500 ; 1.425 ; 2.980 ; ; -1.078 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 0.500 ; 1.425 ; 2.970 ; ; -1.072 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 0.500 ; 1.425 ; 2.964 ; ; -1.071 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 0.500 ; 1.425 ; 2.963 ; ; -1.059 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 0.500 ; 1.425 ; 2.951 ; ; -0.516 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; Reg8:inst|19 ; LOAD ; T4 ; 0.500 ; -0.414 ; 0.569 ; ; -0.373 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; Reg8:inst|17 ; LOAD ; T4 ; 0.500 ; -0.401 ; 0.439 ; ; -0.319 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.711 ; ; -0.281 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.673 ; ; -0.280 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.672 ; ; -0.277 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.669 ; ; -0.272 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.664 ; ; -0.271 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.663 ; ; -0.268 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.660 ; ; -0.252 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 1.000 ; 1.425 ; 2.644 ; ; -0.198 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; Reg8:inst|12 ; LOAD ; T4 ; 0.500 ; -0.412 ; 0.253 ; ; -0.192 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; Reg8:inst|14 ; LOAD ; T4 ; 0.500 ; -0.415 ; 0.244 ; ; -0.188 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; Reg8:inst|18 ; LOAD ; T4 ; 0.500 ; -0.413 ; 0.242 ; ; -0.188 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; Reg8:inst|15 ; LOAD ; T4 ; 0.500 ; -0.414 ; 0.241 ; ; -0.188 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; Reg8:inst|16 ; LOAD ; T4 ; 0.500 ; -0.413 ; 0.242 ; ; -0.174 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; Reg8:inst|13 ; LOAD ; T4 ; 0.500 ; -0.402 ; 0.239 ; ; 0.253 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; Reg8:inst|18 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.660 ; ; 0.258 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; Reg8:inst|12 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.655 ; ; 0.266 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; Reg8:inst|13 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.647 ; ; 0.280 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; Reg8:inst|16 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.633 ; ; 0.283 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; Reg8:inst|19 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.630 ; ; 0.285 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; Reg8:inst|14 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.628 ; ; 0.296 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; Reg8:inst|17 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.617 ; ; 0.297 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; Reg8:inst|15 ; T2 ; T4 ; 1.000 ; -0.054 ; 0.616 ; +--------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'T4' ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ ; 0.341 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; Reg8:inst|17 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.523 ; ; 0.342 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; Reg8:inst|15 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.524 ; ; 0.351 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; Reg8:inst|14 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.533 ; ; 0.360 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; Reg8:inst|16 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.542 ; ; 0.363 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; Reg8:inst|19 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.545 ; ; 0.366 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; Reg8:inst|13 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.548 ; ; 0.373 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; Reg8:inst|12 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.555 ; ; 0.376 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; Reg8:inst|18 ; T2 ; T4 ; 0.000 ; 0.058 ; 0.558 ; ; 0.872 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.477 ; ; 0.878 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; Reg8:inst|13 ; LOAD ; T4 ; -0.500 ; -0.303 ; 0.199 ; ; 0.883 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.488 ; ; 0.887 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; Reg8:inst|15 ; LOAD ; T4 ; -0.500 ; -0.314 ; 0.197 ; ; 0.889 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; Reg8:inst|16 ; LOAD ; T4 ; -0.500 ; -0.312 ; 0.201 ; ; 0.890 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; Reg8:inst|18 ; LOAD ; T4 ; -0.500 ; -0.313 ; 0.201 ; ; 0.892 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; Reg8:inst|14 ; LOAD ; T4 ; -0.500 ; -0.314 ; 0.202 ; ; 0.893 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.498 ; ; 0.897 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.502 ; ; 0.900 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; Reg8:inst|12 ; LOAD ; T4 ; -0.500 ; -0.312 ; 0.212 ; ; 0.909 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.514 ; ; 0.912 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.517 ; ; 0.917 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.522 ; ; 0.926 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; 0.000 ; 1.481 ; 2.531 ; ; 1.048 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; Reg8:inst|17 ; LOAD ; T4 ; -0.500 ; -0.301 ; 0.371 ; ; 1.186 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; Reg8:inst|19 ; LOAD ; T4 ; -0.500 ; -0.314 ; 0.496 ; ; 1.563 ; LOAD ; Reg8:inst|13 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.668 ; ; 1.577 ; LOAD ; Reg8:inst|17 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.682 ; ; 1.581 ; LOAD ; Reg8:inst|15 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.686 ; ; 1.582 ; LOAD ; Reg8:inst|18 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.687 ; ; 1.582 ; LOAD ; Reg8:inst|14 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.687 ; ; 1.584 ; LOAD ; Reg8:inst|12 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.689 ; ; 1.585 ; LOAD ; Reg8:inst|16 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.690 ; ; 1.711 ; LOAD ; Reg8:inst|19 ; LOAD ; T4 ; -0.500 ; 1.481 ; 2.816 ; +-------+-------------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'T2' ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 0.727 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.039 ; 0.850 ; ; 0.795 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; T2 ; T2 ; 0.000 ; 0.039 ; 0.918 ; ; 0.877 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.000 ; ; 0.900 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; -0.500 ; -0.316 ; 0.208 ; ; 0.964 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.087 ; ; 0.970 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.093 ; ; 0.985 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.108 ; ; 0.989 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; -0.316 ; 0.297 ; ; 0.992 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.115 ; ; 1.004 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[7]~8 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.314 ; 0.314 ; ; 1.018 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; -0.315 ; 0.327 ; ; 1.019 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.142 ; ; 1.020 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.143 ; ; 1.024 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.147 ; ; 1.033 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; -0.316 ; 0.341 ; ; 1.041 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.164 ; ; 1.047 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.170 ; ; 1.050 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; -0.303 ; 0.371 ; ; 1.052 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.175 ; ; 1.055 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; -0.305 ; 0.374 ; ; 1.070 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.193 ; ; 1.071 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.194 ; ; 1.087 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.210 ; ; 1.106 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.229 ; ; 1.106 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.229 ; ; 1.107 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.230 ; ; 1.108 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.231 ; ; 1.113 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.236 ; ; 1.134 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.257 ; ; 1.136 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.259 ; ; 1.141 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.264 ; ; 1.160 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.283 ; ; 1.164 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.287 ; ; 1.170 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.293 ; ; 1.183 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.306 ; ; 1.189 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.312 ; ; 1.190 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.313 ; ; 1.196 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.319 ; ; 1.219 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.342 ; ; 1.225 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.348 ; ; 1.253 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.376 ; ; 1.279 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.402 ; ; 1.302 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; T2 ; T2 ; 0.000 ; 0.039 ; 1.425 ; ; 1.438 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; -0.314 ; 0.748 ; ; 1.611 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[6]~9 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.305 ; 0.930 ; ; 1.634 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; -0.316 ; 0.942 ; ; 1.670 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; -0.316 ; 0.978 ; ; 1.673 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; -0.315 ; 0.982 ; ; 1.675 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; -0.316 ; 0.983 ; ; 1.678 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; -0.315 ; 0.987 ; ; 1.702 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; -0.303 ; 1.023 ; ; 1.706 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; -0.315 ; 1.015 ; ; 1.718 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; -0.314 ; 1.028 ; ; 1.725 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; -0.315 ; 1.034 ; ; 1.730 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; -0.303 ; 1.051 ; ; 1.736 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.044 ; ; 1.749 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; -0.303 ; 1.070 ; ; 1.753 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[4]~11 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.061 ; ; 1.761 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; -0.315 ; 1.070 ; ; 1.765 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; -0.314 ; 1.075 ; ; 1.785 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.093 ; ; 1.785 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; -0.303 ; 1.106 ; ; 1.790 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.098 ; ; 1.794 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[5]~10 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.102 ; ; 1.801 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; -0.314 ; 1.111 ; ; 1.818 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.126 ; ; 1.837 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.145 ; ; 1.844 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[1]~14 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.315 ; 1.153 ; ; 1.868 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[2]~13 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.303 ; 1.189 ; ; 1.873 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.181 ; ; 1.884 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[3]~12 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.314 ; 1.194 ; ; 1.956 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|latch_signal[0]~15 ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; -0.316 ; 1.264 ; +-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Recovery: 'T2' ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -1.001 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.891 ; ; -1.001 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.891 ; ; -1.001 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.891 ; ; -1.001 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.891 ; ; -0.990 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.880 ; ; -0.990 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.880 ; ; -0.990 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.880 ; ; -0.894 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.500 ; 1.423 ; 2.784 ; ; -0.166 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.556 ; ; -0.166 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.556 ; ; -0.166 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.556 ; ; -0.166 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.556 ; ; -0.159 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.549 ; ; -0.159 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.549 ; ; -0.159 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.549 ; ; -0.070 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 1.000 ; 1.423 ; 2.460 ; +--------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Removal: 'T2' ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 0.768 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.371 ; ; 0.853 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.456 ; ; 0.853 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.456 ; ; 0.853 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.456 ; ; 0.860 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.463 ; ; 0.860 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.463 ; ; 0.860 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.463 ; ; 0.860 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; 0.000 ; 1.479 ; 2.463 ; ; 1.589 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[6] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.692 ; ; 1.682 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[3] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.785 ; ; 1.682 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[5] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.785 ; ; 1.682 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[7] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.785 ; ; 1.693 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[0] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.796 ; ; 1.693 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[1] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.796 ; ; 1.693 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[2] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.796 ; ; 1.693 ; LOAD ; lpm_counter0:inst5|lpm_counter:LPM_COUNTER_component|cntr_b6j:auto_generated|counter_reg_bit[4] ; LOAD ; T2 ; -0.500 ; 1.479 ; 2.796 ; +-------+-----------+-------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ---------------------------------------------- ; Fast 1200mV 0C Model Metastability Summary ; ---------------------------------------------- No synchronizer chains to report. +-------------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +------------------+---------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +------------------+---------+-------+----------+---------+---------------------+ ; Worst-case Slack ; -3.359 ; 0.341 ; -2.360 ; 0.768 ; -3.000 ; ; LOAD ; N/A ; N/A ; N/A ; N/A ; -3.000 ; ; T2 ; -3.359 ; 0.571 ; -2.360 ; 0.768 ; -3.000 ; ; T4 ; -2.795 ; 0.341 ; N/A ; N/A ; -3.000 ; ; Design-wide TNS ; -43.962 ; 0.0 ; -18.581 ; 0.0 ; -32.792 ; ; LOAD ; N/A ; N/A ; N/A ; N/A ; -3.000 ; ; T2 ; -22.917 ; 0.000 ; -18.581 ; 0.000 ; -14.896 ; ; T4 ; -21.045 ; 0.000 ; N/A ; N/A ; -14.896 ; +------------------+---------+-------+----------+---------+---------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Q[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Q[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Q[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Q[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Q[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Q[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Q[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Q[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +----------------------------------------------------------------------------+ ; Input Transition Times ; +-------------------------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-------------------------+--------------+-----------------+-----------------+ ; PC_B ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[7] ; 2.5 V ; 2000 ps ; 2000 ps ; ; LOAD ; 2.5 V ; 2000 ps ; 2000 ps ; ; CLR ; 2.5 V ; 2000 ps ; 2000 ps ; ; T4 ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[6] ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[5] ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[4] ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[3] ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[2] ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[1] ; 2.5 V ; 2000 ps ; 2000 ps ; ; D[0] ; 2.5 V ; 2000 ps ; 2000 ps ; ; T2 ; 2.5 V ; 2000 ps ; 2000 ps ; ; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; ; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; ; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; +-------------------------+--------------+-----------------+-----------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 0c Model) ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Q[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; Q[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; Q[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; Q[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; Q[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; Q[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; Q[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; Q[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; ; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; ; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 85c Model) ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Q[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; Q[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; Q[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; Q[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; Q[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; Q[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; Q[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; Q[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; ; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; ; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1200mv 0c Model) ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Q[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; Q[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; Q[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; Q[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; Q[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; Q[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; Q[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; Q[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; ; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; ; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-------------------------------------------------------------------+ ; Setup Transfers ; +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ ; LOAD ; T2 ; 0 ; 44 ; 0 ; 0 ; ; T2 ; T2 ; 36 ; 0 ; 0 ; 0 ; ; LOAD ; T4 ; 16 ; 24 ; 0 ; 0 ; ; T2 ; T4 ; 8 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------+ ; Hold Transfers ; +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ ; LOAD ; T2 ; 0 ; 44 ; 0 ; 0 ; ; T2 ; T2 ; 36 ; 0 ; 0 ; 0 ; ; LOAD ; T4 ; 16 ; 24 ; 0 ; 0 ; ; T2 ; T4 ; 8 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------+ ; Recovery Transfers ; +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ ; LOAD ; T2 ; 8 ; 8 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------+ ; Removal Transfers ; +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ ; LOAD ; T2 ; 8 ; 8 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths Summary ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 10 ; 10 ; ; Unconstrained Input Port Paths ; 48 ; 48 ; ; Unconstrained Output Ports ; 8 ; 8 ; ; Unconstrained Output Port Paths ; 8 ; 8 ; +---------------------------------+-------+------+ +-------------------------------------+ ; Clock Status Summary ; +--------+-------+------+-------------+ ; Target ; Clock ; Type ; Status ; +--------+-------+------+-------------+ ; LOAD ; LOAD ; Base ; Constrained ; ; T2 ; T2 ; Base ; Constrained ; ; T4 ; T4 ; Base ; Constrained ; +--------+-------+------+-------------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; CLR ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; PC_B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; Q[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; CLR ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; D[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; PC_B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +-------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +-------------+---------------------------------------------------------------------------------------+ ; Q[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; Q[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Processing started: Tue Oct 24 14:35:59 2023 Info: Command: quartus_sta PC_AR2627 -c PC_AR2627 Info: qsta_default_script.tcl version: #3 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Warning (335093): TimeQuest Timing Analyzer is analyzing 8 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. Critical Warning (332012): Synopsys Design Constraints File file not found: 'PC_AR2627.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name T2 T2 Info (332105): create_clock -period 1.000 -name LOAD LOAD Info (332105): create_clock -period 1.000 -name T4 T4 Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -3.359 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.359 -22.917 T2 Info (332119): -2.795 -21.045 T4 Info (332146): Worst-case hold slack is 0.584 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.584 0.000 T4 Info (332119): 0.624 0.000 T2 Info (332146): Worst-case recovery slack is -2.360 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.360 -18.581 T2 Info (332146): Worst-case removal slack is 1.876 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.876 0.000 T2 Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.000 -14.896 T2 Info (332119): -3.000 -14.896 T4 Info (332119): -3.000 -3.000 LOAD Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -3.035 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.035 -20.735 T2 Info (332119): -2.674 -21.011 T4 Info (332146): Worst-case hold slack is 0.535 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.535 0.000 T4 Info (332119): 0.571 0.000 T2 Info (332146): Worst-case recovery slack is -2.230 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.230 -17.575 T2 Info (332146): Worst-case removal slack is 1.778 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.778 0.000 T2 Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.000 -14.896 T2 Info (332119): -3.000 -14.896 T4 Info (332119): -3.000 -3.000 LOAD Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -1.551 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.551 -10.700 T2 Info (332119): -1.172 -8.748 T4 Info (332146): Worst-case hold slack is 0.341 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.341 0.000 T4 Info (332119): 0.727 0.000 T2 Info (332146): Worst-case recovery slack is -1.001 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.001 -7.868 T2 Info (332146): Worst-case removal slack is 0.768 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.768 0.000 T2 Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.000 -11.464 T2 Info (332119): -3.000 -11.456 T4 Info (332119): -3.000 -3.000 LOAD Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings Info: Peak virtual memory: 4923 megabytes Info: Processing ended: Tue Oct 24 14:36:01 2023 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02