$comment File created using the following command: vcd file PC_AR2627.msim.vcd -direction $end $date Tue Oct 24 15:33:38 2023 $end $version ModelSim Version 10.5b $end $timescale 1ps $end $scope module PC_AR2627_vlg_vec_tst $end $var reg 1 ! CLR $end $var reg 8 " D [7:0] $end $var reg 1 # LOAD $end $var reg 1 $ PC_B $end $var reg 1 % T2 $end $var reg 1 & T4 $end $var wire 1 ' Q [7] $end $var wire 1 ( Q [6] $end $var wire 1 ) Q [5] $end $var wire 1 * Q [4] $end $var wire 1 + Q [3] $end $var wire 1 , Q [2] $end $var wire 1 - Q [1] $end $var wire 1 . Q [0] $end $scope module i1 $end $var wire 1 / gnd $end $var wire 1 0 vcc $end $var wire 1 1 unknown $end $var tri1 1 2 devclrn $end $var tri1 1 3 devpor $end $var tri1 1 4 devoe $end $var wire 1 5 Q[7]~output_o $end $var wire 1 6 Q[6]~output_o $end $var wire 1 7 Q[5]~output_o $end $var wire 1 8 Q[4]~output_o $end $var wire 1 9 Q[3]~output_o $end $var wire 1 : Q[2]~output_o $end $var wire 1 ; Q[1]~output_o $end $var wire 1 < Q[0]~output_o $end $var wire 1 = T4~input_o $end $var wire 1 > T4~inputclkctrl_outclk $end $var wire 1 ? CLR~input_o $end $var wire 1 @ LOAD~input_o $end $var wire 1 A PC_B~input_o $end $var wire 1 B inst2|$00000|auto_generated|result_node[7]~30_combout $end $var wire 1 C D[7]~input_o $end $var wire 1 D inst2|$00000|auto_generated|result_node[7]~14_combout $end $var wire 1 E T2~input_o $end $var wire 1 F T2~inputclkctrl_outclk $end $var wire 1 G LOAD~inputclkctrl_outclk $end $var wire 1 H inst5|LPM_COUNTER_component|auto_generated|latch_signal[7]~8_combout $end $var wire 1 I D[5]~input_o $end $var wire 1 J inst5|LPM_COUNTER_component|auto_generated|latch_signal[5]~10_combout $end $var wire 1 K D[4]~input_o $end $var wire 1 L inst5|LPM_COUNTER_component|auto_generated|latch_signal[4]~11_combout $end $var wire 1 M D[3]~input_o $end $var wire 1 N inst5|LPM_COUNTER_component|auto_generated|latch_signal[3]~12_combout $end $var wire 1 O D[2]~input_o $end $var wire 1 P inst5|LPM_COUNTER_component|auto_generated|latch_signal[2]~13_combout $end $var wire 1 Q D[1]~input_o $end $var wire 1 R inst5|LPM_COUNTER_component|auto_generated|latch_signal[1]~14_combout $end $var wire 1 S D[0]~input_o $end $var wire 1 T inst5|LPM_COUNTER_component|auto_generated|latch_signal[0]~15_combout $end $var wire 1 U inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita0~combout $end $var wire 1 V inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[0]~7_combout $end $var wire 1 W inst5|LPM_COUNTER_component|auto_generated|aclr_actual~0_combout $end $var wire 1 X inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita0~COUT $end $var wire 1 Y inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita1~combout $end $var wire 1 Z inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[1]~6_combout $end $var wire 1 [ inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita1~COUT $end $var wire 1 \ inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita2~combout $end $var wire 1 ] inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[2]~5_combout $end $var wire 1 ^ inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita2~COUT $end $var wire 1 _ inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita3~combout $end $var wire 1 ` inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[3]~4_combout $end $var wire 1 a inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita3~COUT $end $var wire 1 b inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita4~combout $end $var wire 1 c inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[4]~3_combout $end $var wire 1 d inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita4~COUT $end $var wire 1 e inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita5~combout $end $var wire 1 f inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[5]~2_combout $end $var wire 1 g inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita5~COUT $end $var wire 1 h inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita6~combout $end $var wire 1 i D[6]~input_o $end $var wire 1 j inst5|LPM_COUNTER_component|auto_generated|latch_signal[6]~9_combout $end $var wire 1 k inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[6]~1_combout $end $var wire 1 l inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita6~COUT $end $var wire 1 m inst5|LPM_COUNTER_component|auto_generated|counter_comb_bita7~combout $end $var wire 1 n inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit[7]~0_combout $end $var wire 1 o inst2|$00000|auto_generated|result_node[7]~15_combout $end $var wire 1 p inst|12~q $end $var wire 1 q inst2|$00000|auto_generated|result_node[6]~16_combout $end $var wire 1 r inst2|$00000|auto_generated|result_node[6]~17_combout $end $var wire 1 s inst|13~q $end $var wire 1 t inst2|$00000|auto_generated|result_node[5]~18_combout $end $var wire 1 u inst2|$00000|auto_generated|result_node[5]~19_combout $end $var wire 1 v inst|14~q $end $var wire 1 w inst2|$00000|auto_generated|result_node[4]~20_combout $end $var wire 1 x inst2|$00000|auto_generated|result_node[4]~21_combout $end $var wire 1 y inst|15~q $end $var wire 1 z inst2|$00000|auto_generated|result_node[3]~22_combout $end $var wire 1 { inst2|$00000|auto_generated|result_node[3]~23_combout $end $var wire 1 | inst|16~q $end $var wire 1 } inst2|$00000|auto_generated|result_node[2]~24_combout $end $var wire 1 ~ inst2|$00000|auto_generated|result_node[2]~25_combout $end $var wire 1 !! inst|17~q $end $var wire 1 "! inst2|$00000|auto_generated|result_node[1]~26_combout $end $var wire 1 #! inst2|$00000|auto_generated|result_node[1]~27_combout $end $var wire 1 $! inst|18~q $end $var wire 1 %! inst2|$00000|auto_generated|result_node[0]~28_combout $end $var wire 1 &! inst2|$00000|auto_generated|result_node[0]~29_combout $end $var wire 1 '! inst|19~q $end $var wire 1 (! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [7] $end $var wire 1 )! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [6] $end $var wire 1 *! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [5] $end $var wire 1 +! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [4] $end $var wire 1 ,! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [3] $end $var wire 1 -! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [2] $end $var wire 1 .! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [1] $end $var wire 1 /! inst5|LPM_COUNTER_component|auto_generated|counter_reg_bit [0] $end $var wire 1 0! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [7] $end $var wire 1 1! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [6] $end $var wire 1 2! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [5] $end $var wire 1 3! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [4] $end $var wire 1 4! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [3] $end $var wire 1 5! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [2] $end $var wire 1 6! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [1] $end $var wire 1 7! inst5|LPM_COUNTER_component|auto_generated|pre_hazard [0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars 1! b0 " 0# 0$ 0% 0& 0. 0- 0, 0+ 0* 0) 0( 0' 0/ 10 x1 12 13 14 05 06 07 08 09 0: 0; 0< 0= 0> 1? 0@ 0A 0B 0C 0D 0E 0F 0G 1H 0I 1J 0K 1L 0M 1N 0O 1P 0Q 1R 0S 1T 1U 1V 1W 0X 0Y 0Z 1[ 0\ 0] 0^ 0_ 0` 1a 0b 0c 0d 0e 0f 1g 0h 0i 1j 0k 0l 0m 0n 0o 0p 0q 0r 0s 0t 0u 0v 0w 0x 0y 0z 0{ 0| 0} 0~ 0!! 0"! 0#! 0$! 0%! 0&! 0'! 0/! 0.! 0-! 0,! 0+! 0*! 0)! 0(! 17! 16! 15! 14! 13! 12! 11! 10! $end #5000 1% 0! 1E 0? 1F 0W 1B #10000 1& 0% 1= 0E 0F 1> #15000 0& 1% 0= 1E 1F 0> 1/! 07! 1X 0U 1&! 1Y 0V 1Z #20000 1& 0% 1= 0E 0F 1> 1'! 1< 1. #25000 0& 1% 0= 1E 1F 0> 1.! 0/! 06! 17! 1#! 0[ 0Y 0X 1U 0&! 1\ 1[ 1Y 0Z 1V 0\ 1] 1Z 0] #30000 1& 0% 1= 0E 0F 1> 0'! 1$! 1; 0< 0. 1- #35000 b1000 " b1010 " 1$ 0& 1Q 1M 1A 0= 0> 1"! 1z 0B 1{ #40000 1& 1= 1> 1| 19 1+ #45000 1% b10 " b0 " 0$ 0& 1E 0Q 0M 0A 0= 0> 1F 0"! 0z 1B 0{ 1/! 07! 1X 0U 1&! 0[ 0Y 0V 1\ 0Z 1] #50000 0% 1& 0E 1= 1> 0F 1'! 0| 09 1< 1. 0+ #55000 1% 0& 1E 0= 0> 1F 1-! 0.! 0/! 05! 16! 17! 1~ 0#! 1^ 0\ 1[ 1Y 0X 1U 0&! 1_ 0^ 1\ 0Y 0] 1Z 1V 0_ 1` 1] 0Z 0` #60000 0% 1& 0E 1= 1> 0F 0'! 0$! 1!! 1: 0; 0< 0. 0- 1, #65000 b1 " b1001 " b1011 " 1$ 0& 1S 1Q 1M 1A 0= 0> 1%! 1"! 1z 0B 1&! 1#! 1{ 0~ #70000 1& 1= 1> 1'! 1$! 0!! 1| 19 0: 1; 1< 1. 1- 0, 1+ #75000 1% b1010 " b10 " b0 " 0$ 0& 1E 0S 0Q 0M 0A 0= 0> 1F 0%! 0"! 0z 1B 0&! 0#! 0{ 1~ 1/! 07! 1X 0U 1&! 1Y 0V 1Z #80000 0% 1& 0E 1= 1> 0F 0$! 1!! 0| 09 1: 0; 0- 1, 0+ #85000 1% 0& 1E 0= 0> 1F 1.! 0/! 06! 17! 1#! 0[ 0Y 0X 1U 0&! 1^ 0\ 1[ 1Y 0Z 1V 1_ 0^ 1\ 0] 1Z 0_ 1` 1] 0` #90000 0% 1& 0E 1= 1> 0F 0'! 1$! 1; 0< 0. 1- #95000 b1 " b1001 " b1011 " 1$ 0& 1S 1Q 1M 1A 0= 0> 1%! 1"! 1z 0B 1&! 1{ 0~ #100000 1& 1= 1> 1'! 0!! 1| 19 0: 1< 1. 0, 1+ #105000 1% b1010 " b10 " b0 " 0$ 0& 1E 0S 0Q 0M 0A 0= 0> 1F 0%! 0"! 0z 1B 0&! 0{ 1~ 1/! 07! 1X 0U 1&! 0[ 0Y 0V 1^ 0\ 0Z 1_ 0] 1` #110000 0% 1& 0E 1= 1> 0F 1!! 0| 09 1: 1, 0+ #115000 1% 0& 1E 0= 0> 1F 1,! 0-! 0.! 0/! 04! 15! 16! 17! 1{ 0~ 0#! 0a 0_ 0^ 1\ 1[ 1Y 0X 1U 0&! 1b 1a 1_ 0\ 0Y 0` 1] 1Z 1V 0b 1c 1` 0] 0Z 0c #120000 1# b1 " 0% 1& 1@ 1S 0E 1= 1G 1> 0F 1%! 1W 0B 0T 07! 1&! 0{ 0V 1X 0U 1Y 1V 1Z 0,! 0'! 0$! 0!! 1| 19 0: 0; 0< 14! 0. 0- 0, 1+ 0_ 0` #125000 1% 0& 1E 0= 0> 1F #130000 0# b0 " 0% 1& 0@ 0S 0E 1= 0G 1> 0F 0%! 0W 1B 1'! 0| 09 1< 1. 0+ #135000 1% 0& 1E 0= 0> 1F 1.! 1/! 06! 17! 1#! 0[ 0Y 0X 1U 0&! 1\ 1[ 1Y 0Z 0V 0\ 1] 1Z 0] #140000