|ram2627
q[0] <= LPM_RAM_DQ:inst.q[0]
q[1] <= LPM_RAM_DQ:inst.q[1]
q[2] <= LPM_RAM_DQ:inst.q[2]
q[3] <= LPM_RAM_DQ:inst.q[3]
q[4] <= LPM_RAM_DQ:inst.q[4]
q[5] <= LPM_RAM_DQ:inst.q[5]
q[6] <= LPM_RAM_DQ:inst.q[6]
q[7] <= LPM_RAM_DQ:inst.q[7]
clock => LPM_RAM_DQ:inst.inclock
we => LPM_RAM_DQ:inst.we
address[0] => LPM_RAM_DQ:inst.address[0]
address[1] => LPM_RAM_DQ:inst.address[1]
address[2] => LPM_RAM_DQ:inst.address[2]
address[3] => LPM_RAM_DQ:inst.address[3]
address[4] => LPM_RAM_DQ:inst.address[4]
address[5] => LPM_RAM_DQ:inst.address[5]
address[6] => LPM_RAM_DQ:inst.address[6]
address[7] => LPM_RAM_DQ:inst.address[7]
data[0] => LPM_RAM_DQ:inst.data[0]
data[1] => LPM_RAM_DQ:inst.data[1]
data[2] => LPM_RAM_DQ:inst.data[2]
data[3] => LPM_RAM_DQ:inst.data[3]
data[4] => LPM_RAM_DQ:inst.data[4]
data[5] => LPM_RAM_DQ:inst.data[5]
data[6] => LPM_RAM_DQ:inst.data[6]
data[7] => LPM_RAM_DQ:inst.data[7]


|ram2627|LPM_RAM_DQ:inst
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]


|ram2627|LPM_RAM_DQ:inst|altram:sram
we => _.IN0
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
data[6] => altsyncram:ram_block.data_a[6]
data[7] => altsyncram:ram_block.data_a[7]
address[0] => altsyncram:ram_block.address_a[0]
address[1] => altsyncram:ram_block.address_a[1]
address[2] => altsyncram:ram_block.address_a[2]
address[3] => altsyncram:ram_block.address_a[3]
address[4] => altsyncram:ram_block.address_a[4]
address[5] => altsyncram:ram_block.address_a[5]
address[6] => altsyncram:ram_block.address_a[6]
address[7] => altsyncram:ram_block.address_a[7]
clocki => altsyncram:ram_block.clock0
clocko => ~NO_FANOUT~
be => _.IN1
q[0] <= altsyncram:ram_block.q_a[0]
q[1] <= altsyncram:ram_block.q_a[1]
q[2] <= altsyncram:ram_block.q_a[2]
q[3] <= altsyncram:ram_block.q_a[3]
q[4] <= altsyncram:ram_block.q_a[4]
q[5] <= altsyncram:ram_block.q_a[5]
q[6] <= altsyncram:ram_block.q_a[6]
q[7] <= altsyncram:ram_block.q_a[7]


|ram2627|LPM_RAM_DQ:inst|altram:sram|altsyncram:ram_block
wren_a => altsyncram_ap71:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_ap71:auto_generated.data_a[0]
data_a[1] => altsyncram_ap71:auto_generated.data_a[1]
data_a[2] => altsyncram_ap71:auto_generated.data_a[2]
data_a[3] => altsyncram_ap71:auto_generated.data_a[3]
data_a[4] => altsyncram_ap71:auto_generated.data_a[4]
data_a[5] => altsyncram_ap71:auto_generated.data_a[5]
data_a[6] => altsyncram_ap71:auto_generated.data_a[6]
data_a[7] => altsyncram_ap71:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ap71:auto_generated.address_a[0]
address_a[1] => altsyncram_ap71:auto_generated.address_a[1]
address_a[2] => altsyncram_ap71:auto_generated.address_a[2]
address_a[3] => altsyncram_ap71:auto_generated.address_a[3]
address_a[4] => altsyncram_ap71:auto_generated.address_a[4]
address_a[5] => altsyncram_ap71:auto_generated.address_a[5]
address_a[6] => altsyncram_ap71:auto_generated.address_a[6]
address_a[7] => altsyncram_ap71:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ap71:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ap71:auto_generated.q_a[0]
q_a[1] <= altsyncram_ap71:auto_generated.q_a[1]
q_a[2] <= altsyncram_ap71:auto_generated.q_a[2]
q_a[3] <= altsyncram_ap71:auto_generated.q_a[3]
q_a[4] <= altsyncram_ap71:auto_generated.q_a[4]
q_a[5] <= altsyncram_ap71:auto_generated.q_a[5]
q_a[6] <= altsyncram_ap71:auto_generated.q_a[6]
q_a[7] <= altsyncram_ap71:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|ram2627|LPM_RAM_DQ:inst|altram:sram|altsyncram:ram_block|altsyncram_ap71:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE