// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition"

// DATE "10/10/2023 00:12:06"

// 
// Device: Altera EP4CE55F23C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module ram2627 (
	q,
	clock,
	we,
	address,
	data);
output 	[7:0] q;
input 	clock;
input 	we;
input 	[7:0] address;
input 	[7:0] data;

// Design Ports Information
// q[7]	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[6]	=>  Location: PIN_A16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[5]	=>  Location: PIN_A9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[4]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[3]	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[2]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[1]	=>  Location: PIN_B9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// q[0]	=>  Location: PIN_E12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// we	=>  Location: PIN_G13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// clock	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[7]	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[0]	=>  Location: PIN_A10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[1]	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[2]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[3]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[4]	=>  Location: PIN_B15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[5]	=>  Location: PIN_B10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[6]	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// address[7]	=>  Location: PIN_B16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[6]	=>  Location: PIN_C15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[5]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[4]	=>  Location: PIN_B14,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[3]	=>  Location: PIN_D13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[2]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[1]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// data[0]	=>  Location: PIN_A14,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \q[7]~output_o ;
wire \q[6]~output_o ;
wire \q[5]~output_o ;
wire \q[4]~output_o ;
wire \q[3]~output_o ;
wire \q[2]~output_o ;
wire \q[1]~output_o ;
wire \q[0]~output_o ;
wire \we~input_o ;
wire \clock~input_o ;
wire \clock~inputclkctrl_outclk ;
wire \data[0]~input_o ;
wire \address[0]~input_o ;
wire \address[1]~input_o ;
wire \address[2]~input_o ;
wire \address[3]~input_o ;
wire \address[4]~input_o ;
wire \address[5]~input_o ;
wire \address[6]~input_o ;
wire \address[7]~input_o ;
wire \data[1]~input_o ;
wire \data[2]~input_o ;
wire \data[3]~input_o ;
wire \data[4]~input_o ;
wire \data[5]~input_o ;
wire \data[6]~input_o ;
wire \data[7]~input_o ;
wire [7:0] \inst|sram|ram_block|auto_generated|q_a ;

wire [17:0] \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

assign \inst|sram|ram_block|auto_generated|q_a [0] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \inst|sram|ram_block|auto_generated|q_a [1] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \inst|sram|ram_block|auto_generated|q_a [2] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \inst|sram|ram_block|auto_generated|q_a [3] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \inst|sram|ram_block|auto_generated|q_a [4] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \inst|sram|ram_block|auto_generated|q_a [5] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \inst|sram|ram_block|auto_generated|q_a [6] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \inst|sram|ram_block|auto_generated|q_a [7] = \inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];

hard_block auto_generated_inst(
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// Location: IOOBUF_X41_Y53_N9
cycloneive_io_obuf \q[7]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [7]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[7]~output .bus_hold = "false";
defparam \q[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X55_Y53_N23
cycloneive_io_obuf \q[6]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [6]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[6]~output .bus_hold = "false";
defparam \q[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X35_Y53_N2
cycloneive_io_obuf \q[5]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [5]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[5]~output .bus_hold = "false";
defparam \q[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X37_Y53_N2
cycloneive_io_obuf \q[4]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [4]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[4]~output .bus_hold = "false";
defparam \q[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X55_Y53_N16
cycloneive_io_obuf \q[3]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [3]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[3]~output .bus_hold = "false";
defparam \q[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X37_Y53_N9
cycloneive_io_obuf \q[2]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [2]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[2]~output .bus_hold = "false";
defparam \q[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X35_Y53_N9
cycloneive_io_obuf \q[1]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [1]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[1]~output .bus_hold = "false";
defparam \q[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X41_Y53_N2
cycloneive_io_obuf \q[0]~output (
	.i(\inst|sram|ram_block|auto_generated|q_a [0]),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\q[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[0]~output .bus_hold = "false";
defparam \q[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X55_Y53_N1
cycloneive_io_ibuf \we~input (
	.i(we),
	.ibar(gnd),
	.o(\we~input_o ));
// synopsys translate_off
defparam \we~input .bus_hold = "false";
defparam \we~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y26_N8
cycloneive_io_ibuf \clock~input (
	.i(clock),
	.ibar(gnd),
	.o(\clock~input_o ));
// synopsys translate_off
defparam \clock~input .bus_hold = "false";
defparam \clock~input .simulate_z_as = "z";
// synopsys translate_on

// Location: CLKCTRL_G2
cycloneive_clkctrl \clock~inputclkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\clock~input_o }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clock~inputclkctrl_outclk ));
// synopsys translate_off
defparam \clock~inputclkctrl .clock_type = "global clock";
defparam \clock~inputclkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: IOIBUF_X43_Y53_N1
cycloneive_io_ibuf \data[0]~input (
	.i(data[0]),
	.ibar(gnd),
	.o(\data[0]~input_o ));
// synopsys translate_off
defparam \data[0]~input .bus_hold = "false";
defparam \data[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X37_Y53_N15
cycloneive_io_ibuf \address[0]~input (
	.i(address[0]),
	.ibar(gnd),
	.o(\address[0]~input_o ));
// synopsys translate_off
defparam \address[0]~input .bus_hold = "false";
defparam \address[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X45_Y53_N22
cycloneive_io_ibuf \address[1]~input (
	.i(address[1]),
	.ibar(gnd),
	.o(\address[1]~input_o ));
// synopsys translate_off
defparam \address[1]~input .bus_hold = "false";
defparam \address[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X41_Y53_N22
cycloneive_io_ibuf \address[2]~input (
	.i(address[2]),
	.ibar(gnd),
	.o(\address[2]~input_o ));
// synopsys translate_off
defparam \address[2]~input .bus_hold = "false";
defparam \address[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X43_Y53_N22
cycloneive_io_ibuf \address[3]~input (
	.i(address[3]),
	.ibar(gnd),
	.o(\address[3]~input_o ));
// synopsys translate_off
defparam \address[3]~input .bus_hold = "false";
defparam \address[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X48_Y53_N8
cycloneive_io_ibuf \address[4]~input (
	.i(address[4]),
	.ibar(gnd),
	.o(\address[4]~input_o ));
// synopsys translate_off
defparam \address[4]~input .bus_hold = "false";
defparam \address[4]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X37_Y53_N22
cycloneive_io_ibuf \address[5]~input (
	.i(address[5]),
	.ibar(gnd),
	.o(\address[5]~input_o ));
// synopsys translate_off
defparam \address[5]~input .bus_hold = "false";
defparam \address[5]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X48_Y53_N1
cycloneive_io_ibuf \address[6]~input (
	.i(address[6]),
	.ibar(gnd),
	.o(\address[6]~input_o ));
// synopsys translate_off
defparam \address[6]~input .bus_hold = "false";
defparam \address[6]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X52_Y53_N1
cycloneive_io_ibuf \address[7]~input (
	.i(address[7]),
	.ibar(gnd),
	.o(\address[7]~input_o ));
// synopsys translate_off
defparam \address[7]~input .bus_hold = "false";
defparam \address[7]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X48_Y53_N15
cycloneive_io_ibuf \data[1]~input (
	.i(data[1]),
	.ibar(gnd),
	.o(\data[1]~input_o ));
// synopsys translate_off
defparam \data[1]~input .bus_hold = "false";
defparam \data[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X43_Y53_N15
cycloneive_io_ibuf \data[2]~input (
	.i(data[2]),
	.ibar(gnd),
	.o(\data[2]~input_o ));
// synopsys translate_off
defparam \data[2]~input .bus_hold = "false";
defparam \data[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X48_Y53_N22
cycloneive_io_ibuf \data[3]~input (
	.i(data[3]),
	.ibar(gnd),
	.o(\data[3]~input_o ));
// synopsys translate_off
defparam \data[3]~input .bus_hold = "false";
defparam \data[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X43_Y53_N8
cycloneive_io_ibuf \data[4]~input (
	.i(data[4]),
	.ibar(gnd),
	.o(\data[4]~input_o ));
// synopsys translate_off
defparam \data[4]~input .bus_hold = "false";
defparam \data[4]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X50_Y53_N22
cycloneive_io_ibuf \data[5]~input (
	.i(data[5]),
	.ibar(gnd),
	.o(\data[5]~input_o ));
// synopsys translate_off
defparam \data[5]~input .bus_hold = "false";
defparam \data[5]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X50_Y53_N1
cycloneive_io_ibuf \data[6]~input (
	.i(data[6]),
	.ibar(gnd),
	.o(\data[6]~input_o ));
// synopsys translate_off
defparam \data[6]~input .bus_hold = "false";
defparam \data[6]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X50_Y53_N15
cycloneive_io_ibuf \data[7]~input (
	.i(data[7]),
	.ibar(gnd),
	.o(\data[7]~input_o ));
// synopsys translate_off
defparam \data[7]~input .bus_hold = "false";
defparam \data[7]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: M9K_X47_Y52_N0
cycloneive_ram_block \inst|sram|ram_block|auto_generated|ram_block1a0 (
	.portawe(\we~input_o ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\clock~inputclkctrl_outclk ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\data[7]~input_o ,\data[6]~input_o ,\data[5]~input_o ,\data[4]~input_o ,\data[3]~input_o ,\data[2]~input_o ,\data[1]~input_o ,\data[0]~input_o }),
	.portaaddr({\address[7]~input_o ,\address[6]~input_o ,\address[5]~input_o ,\address[4]~input_o ,\address[3]~input_o ,\address[2]~input_o ,\address[1]~input_o ,\address[0]~input_o }),
	.portabyteenamasks(1'b1),
	.portbdatain(18'b000000000000000000),
	.portbaddr(8'b00000000),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\inst|sram|ram_block|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .logical_ram_name = "lpm_ram_dq:inst|altram:sram|altsyncram:ram_block|altsyncram_ap71:auto_generated|ALTSYNCRAM";
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .operation_mode = "single_port";
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_address_width = 8;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_data_width = 18;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_last_address = 255;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 256;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_b_address_width = 8;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .port_b_data_width = 18;
defparam \inst|sram|ram_block|auto_generated|ram_block1a0 .ram_block_type = "M9K";
// synopsys translate_on

assign q[7] = \q[7]~output_o ;

assign q[6] = \q[6]~output_o ;

assign q[5] = \q[5]~output_o ;

assign q[4] = \q[4]~output_o ;

assign q[3] = \q[3]~output_o ;

assign q[2] = \q[2]~output_o ;

assign q[1] = \q[1]~output_o ;

assign q[0] = \q[0]~output_o ;

endmodule

module hard_block (

	devpor,
	devclrn,
	devoe);

// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_D1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_K2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_K1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_K22,	 I/O Standard: 2.5 V,	 Current Strength: 8mA

input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

wire \~ALTERA_ASDO_DATA1~~padout ;
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
wire \~ALTERA_DATA0~~padout ;
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
wire \~ALTERA_DATA0~~ibuf_o ;


endmodule