{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1696865835665 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1696865835673 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 09 23:37:15 2023 " "Processing started: Mon Oct 09 23:37:15 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1696865835673 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1696865835673 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rom2627 -c rom2627 " "Command: quartus_map --read_settings_files=on --write_settings_files=off rom2627 -c rom2627" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1696865835673 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1696865835981 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1696865835981 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom2627.bdf 1 1 " "Found 1 design units, including 1 entities, in source file rom2627.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 rom2627 " "Found entity 1: rom2627" {  } { { "rom2627.bdf" "" { Schematic "D:/Projects/quartus/rom/rom2627.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1696865844423 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1696865844423 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "rom2627 " "Elaborating entity \"rom2627\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1696865844444 ""}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "LPM_FILE ucode.hex " "Can't find a definition for parameter LPM_FILE -- assuming ucode.hex was intended to be a quoted string" {  } { { "rom2627.bdf" "" { Schematic "D:/Projects/quartus/rom/rom2627.bdf" { { 328 336 448 424 "inst" "" } } } }  } 0 275006 "Can't find a definition for parameter %1!s! -- assuming %2!s! was intended to be a quoted string" 0 0 "Analysis & Synthesis" 0 -1 1696865844445 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM LPM_ROM:inst " "Elaborating entity \"LPM_ROM\" for hierarchy \"LPM_ROM:inst\"" {  } { { "rom2627.bdf" "inst" { Schematic "D:/Projects/quartus/rom/rom2627.bdf" { { 328 336 448 424 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865844475 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LPM_ROM:inst " "Elaborated megafunction instantiation \"LPM_ROM:inst\"" {  } { { "rom2627.bdf" "" { Schematic "D:/Projects/quartus/rom/rom2627.bdf" { { 328 336 448 424 "inst" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865844482 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LPM_ROM:inst " "Instantiated megafunction \"LPM_ROM:inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE ucode.hex " "Parameter \"LPM_FILE\" = \"ucode.hex\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1696865844483 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1696865844483 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 24 " "Parameter \"LPM_WIDTH\" = \"24\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1696865844483 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 6 " "Parameter \"LPM_WIDTHAD\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1696865844483 ""}  } { { "rom2627.bdf" "" { Schematic "D:/Projects/quartus/rom/rom2627.bdf" { { 328 336 448 424 "inst" "" } } } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1696865844483 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom LPM_ROM:inst\|altrom:srom " "Elaborating entity \"altrom\" for hierarchy \"LPM_ROM:inst\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865844539 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_ROM:inst\|altrom:srom LPM_ROM:inst " "Elaborated megafunction instantiation \"LPM_ROM:inst\|altrom:srom\", which is child of megafunction instantiation \"LPM_ROM:inst\"" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } } { "rom2627.bdf" "" { Schematic "D:/Projects/quartus/rom/rom2627.bdf" { { 328 336 448 424 "inst" "" } } } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865844549 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block " "Elaborating entity \"altsyncram\" for hierarchy \"LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.tdf" 88 6 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865844602 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block LPM_ROM:inst " "Elaborated megafunction instantiation \"LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\", which is child of megafunction instantiation \"LPM_ROM:inst\"" {  } { { "altrom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.tdf" 88 6 0 } } { "rom2627.bdf" "" { Schematic "D:/Projects/quartus/rom/rom2627.bdf" { { 328 336 448 424 "inst" "" } } } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865844613 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2501.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_2501.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2501 " "Found entity 1: altsyncram_2501" {  } { { "db/altsyncram_2501.tdf" "" { Text "D:/Projects/quartus/rom/db/altsyncram_2501.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1696865844657 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1696865844657 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2501 LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_2501:auto_generated " "Elaborating entity \"altsyncram_2501\" for hierarchy \"LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_2501:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865844658 ""}
{ "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI_HDR" "" "Always-enabled tri-state buffer(s) removed" { { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[23\] q\[23\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[23\]\" to the node \"q\[23\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[22\] q\[22\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[22\]\" to the node \"q\[22\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[21\] q\[21\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[21\]\" to the node \"q\[21\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[20\] q\[20\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[20\]\" to the node \"q\[20\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[19\] q\[19\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[19\]\" to the node \"q\[19\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[18\] q\[18\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[18\]\" to the node \"q\[18\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[17\] q\[17\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[17\]\" to the node \"q\[17\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[16\] q\[16\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[16\]\" to the node \"q\[16\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[15\] q\[15\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[15\]\" to the node \"q\[15\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[14\] q\[14\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[14\]\" to the node \"q\[14\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[13\] q\[13\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[13\]\" to the node \"q\[13\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[12\] q\[12\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[12\]\" to the node \"q\[12\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[11\] q\[11\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[11\]\" to the node \"q\[11\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[10\] q\[10\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[10\]\" to the node \"q\[10\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[9\] q\[9\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[9\]\" to the node \"q\[9\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[8\] q\[8\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[8\]\" to the node \"q\[8\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[7\] q\[7\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[7\]\" to the node \"q\[7\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[6\] q\[6\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[6\]\" to the node \"q\[6\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[5\] q\[5\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[5\]\" to the node \"q\[5\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[4\] q\[4\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[4\]\" to the node \"q\[4\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[3\] q\[3\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[3\]\" to the node \"q\[3\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[2\] q\[2\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[2\]\" to the node \"q\[2\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[1\] q\[1\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[1\]\" to the node \"q\[1\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""} { "Warning" "WMLS_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:inst\|otri\[0\] q\[0\] " "Converted the fanout from the always-enabled tri-state buffer \"lpm_rom:inst\|otri\[0\]\" to the node \"q\[0\]\" into a wire" {  } { { "lpm_rom.tdf" "" { Text "d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf" 67 6 0 } }  } 0 13045 "Converted the fanout from the always-enabled tri-state buffer \"%1!s!\" to the node \"%2!s!\" into a wire" 0 0 "Design Software" 0 -1 1696865845026 ""}  } {  } 0 13044 "Always-enabled tri-state buffer(s) removed" 0 0 "Analysis & Synthesis" 0 -1 1696865845026 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1696865845142 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1696865845142 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "55 " "Implemented 55 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Implemented 7 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1696865845198 ""} { "Info" "ICUT_CUT_TM_OPINS" "24 " "Implemented 24 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1696865845198 ""} { "Info" "ICUT_CUT_TM_RAMS" "24 " "Implemented 24 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1696865845198 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1696865845198 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 27 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 27 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4754 " "Peak virtual memory: 4754 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1696865845209 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 09 23:37:25 2023 " "Processing ended: Mon Oct 09 23:37:25 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1696865845209 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1696865845209 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:19 " "Total CPU time (on all processors): 00:00:19" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1696865845209 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1696865845209 ""}