$comment File created using the following command: vcd file rom2627.msim.vcd -direction $end $date Mon Oct 09 23:39:02 2023 $end $version ModelSim Version 10.5b $end $timescale 1ps $end $scope module rom2627_vlg_vec_tst $end $var reg 6 ! address [5:0] $end $var reg 1 " clock $end $var wire 1 # q [23] $end $var wire 1 $ q [22] $end $var wire 1 % q [21] $end $var wire 1 & q [20] $end $var wire 1 ' q [19] $end $var wire 1 ( q [18] $end $var wire 1 ) q [17] $end $var wire 1 * q [16] $end $var wire 1 + q [15] $end $var wire 1 , q [14] $end $var wire 1 - q [13] $end $var wire 1 . q [12] $end $var wire 1 / q [11] $end $var wire 1 0 q [10] $end $var wire 1 1 q [9] $end $var wire 1 2 q [8] $end $var wire 1 3 q [7] $end $var wire 1 4 q [6] $end $var wire 1 5 q [5] $end $var wire 1 6 q [4] $end $var wire 1 7 q [3] $end $var wire 1 8 q [2] $end $var wire 1 9 q [1] $end $var wire 1 : q [0] $end $scope module i1 $end $var wire 1 ; gnd $end $var wire 1 < vcc $end $var wire 1 = unknown $end $var tri1 1 > devclrn $end $var tri1 1 ? devpor $end $var tri1 1 @ devoe $end $var wire 1 A q[23]~output_o $end $var wire 1 B q[22]~output_o $end $var wire 1 C q[21]~output_o $end $var wire 1 D q[20]~output_o $end $var wire 1 E q[19]~output_o $end $var wire 1 F q[18]~output_o $end $var wire 1 G q[17]~output_o $end $var wire 1 H q[16]~output_o $end $var wire 1 I q[15]~output_o $end $var wire 1 J q[14]~output_o $end $var wire 1 K q[13]~output_o $end $var wire 1 L q[12]~output_o $end $var wire 1 M q[11]~output_o $end $var wire 1 N q[10]~output_o $end $var wire 1 O q[9]~output_o $end $var wire 1 P q[8]~output_o $end $var wire 1 Q q[7]~output_o $end $var wire 1 R q[6]~output_o $end $var wire 1 S q[5]~output_o $end $var wire 1 T q[4]~output_o $end $var wire 1 U q[3]~output_o $end $var wire 1 V q[2]~output_o $end $var wire 1 W q[1]~output_o $end $var wire 1 X q[0]~output_o $end $var wire 1 Y clock~input_o $end $var wire 1 Z clock~inputclkctrl_outclk $end $var wire 1 [ address[0]~input_o $end $var wire 1 \ address[1]~input_o $end $var wire 1 ] address[2]~input_o $end $var wire 1 ^ address[3]~input_o $end $var wire 1 _ address[4]~input_o $end $var wire 1 ` address[5]~input_o $end $var wire 1 a inst|srom|rom_block|auto_generated|q_a [23] $end $var wire 1 b inst|srom|rom_block|auto_generated|q_a [22] $end $var wire 1 c inst|srom|rom_block|auto_generated|q_a [21] $end $var wire 1 d inst|srom|rom_block|auto_generated|q_a [20] $end $var wire 1 e inst|srom|rom_block|auto_generated|q_a [19] $end $var wire 1 f inst|srom|rom_block|auto_generated|q_a [18] $end $var wire 1 g inst|srom|rom_block|auto_generated|q_a [17] $end $var wire 1 h inst|srom|rom_block|auto_generated|q_a [16] $end $var wire 1 i inst|srom|rom_block|auto_generated|q_a [15] $end $var wire 1 j inst|srom|rom_block|auto_generated|q_a [14] $end $var wire 1 k inst|srom|rom_block|auto_generated|q_a [13] $end $var wire 1 l inst|srom|rom_block|auto_generated|q_a [12] $end $var wire 1 m inst|srom|rom_block|auto_generated|q_a [11] $end $var wire 1 n inst|srom|rom_block|auto_generated|q_a [10] $end $var wire 1 o inst|srom|rom_block|auto_generated|q_a [9] $end $var wire 1 p inst|srom|rom_block|auto_generated|q_a [8] $end $var wire 1 q inst|srom|rom_block|auto_generated|q_a [7] $end $var wire 1 r inst|srom|rom_block|auto_generated|q_a [6] $end $var wire 1 s inst|srom|rom_block|auto_generated|q_a [5] $end $var wire 1 t inst|srom|rom_block|auto_generated|q_a [4] $end $var wire 1 u inst|srom|rom_block|auto_generated|q_a [3] $end $var wire 1 v inst|srom|rom_block|auto_generated|q_a [2] $end $var wire 1 w inst|srom|rom_block|auto_generated|q_a [1] $end $var wire 1 x inst|srom|rom_block|auto_generated|q_a [0] $end $var wire 1 y inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [35] $end $var wire 1 z inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [34] $end $var wire 1 { inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [33] $end $var wire 1 | inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [32] $end $var wire 1 } inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [31] $end $var wire 1 ~ inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [30] $end $var wire 1 !! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [29] $end $var wire 1 "! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [28] $end $var wire 1 #! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [27] $end $var wire 1 $! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [26] $end $var wire 1 %! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [25] $end $var wire 1 &! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [24] $end $var wire 1 '! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [23] $end $var wire 1 (! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [22] $end $var wire 1 )! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [21] $end $var wire 1 *! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [20] $end $var wire 1 +! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [19] $end $var wire 1 ,! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [18] $end $var wire 1 -! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [17] $end $var wire 1 .! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [16] $end $var wire 1 /! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [15] $end $var wire 1 0! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [14] $end $var wire 1 1! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [13] $end $var wire 1 2! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [12] $end $var wire 1 3! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [11] $end $var wire 1 4! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [10] $end $var wire 1 5! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [9] $end $var wire 1 6! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [8] $end $var wire 1 7! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [7] $end $var wire 1 8! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [6] $end $var wire 1 9! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [5] $end $var wire 1 :! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [4] $end $var wire 1 ;! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [3] $end $var wire 1 ! inst|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus [0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b0 ! 0" 0: 09 08 07 06 05 04 03 02 01 00 0/ 0. 0- 0, 0+ 0* 0) 0( 0' 0& 0% 0$ 0# 0; 1< x= 1> 1? 1@ 0A 0B 0C 0D 0E 0F 0G 0H 0I 0J 0K 0L 0M 0N 0O 0P 0Q 0R 0S 0T 0U 0V 0W 0X 0Y 0Z 0[ 0\ 0] 0^ 0_ 0` 0x 0w 0v 0u 0t 0s 0r 0q 0p 0o 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0>! 0=! 0