vendor_name = ModelSim
source_file = 1, D:/Projects/quartus/rom/rom2627.bdf
source_file = 1, D:/Projects/quartus/rom/ucode.hex
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_rom.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/aglobal171.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altrom.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/others/maxplus2/memmodes.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/a_rdenreg.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altram.inc
source_file = 1, d:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, D:/Projects/quartus/rom/db/altsyncram_2501.tdf
design_name = rom2627
instance = comp, \q[23]~output , q[23]~output, rom2627, 1
instance = comp, \q[22]~output , q[22]~output, rom2627, 1
instance = comp, \q[21]~output , q[21]~output, rom2627, 1
instance = comp, \q[20]~output , q[20]~output, rom2627, 1
instance = comp, \q[19]~output , q[19]~output, rom2627, 1
instance = comp, \q[18]~output , q[18]~output, rom2627, 1
instance = comp, \q[17]~output , q[17]~output, rom2627, 1
instance = comp, \q[16]~output , q[16]~output, rom2627, 1
instance = comp, \q[15]~output , q[15]~output, rom2627, 1
instance = comp, \q[14]~output , q[14]~output, rom2627, 1
instance = comp, \q[13]~output , q[13]~output, rom2627, 1
instance = comp, \q[12]~output , q[12]~output, rom2627, 1
instance = comp, \q[11]~output , q[11]~output, rom2627, 1
instance = comp, \q[10]~output , q[10]~output, rom2627, 1
instance = comp, \q[9]~output , q[9]~output, rom2627, 1
instance = comp, \q[8]~output , q[8]~output, rom2627, 1
instance = comp, \q[7]~output , q[7]~output, rom2627, 1
instance = comp, \q[6]~output , q[6]~output, rom2627, 1
instance = comp, \q[5]~output , q[5]~output, rom2627, 1
instance = comp, \q[4]~output , q[4]~output, rom2627, 1
instance = comp, \q[3]~output , q[3]~output, rom2627, 1
instance = comp, \q[2]~output , q[2]~output, rom2627, 1
instance = comp, \q[1]~output , q[1]~output, rom2627, 1
instance = comp, \q[0]~output , q[0]~output, rom2627, 1
instance = comp, \clock~input , clock~input, rom2627, 1
instance = comp, \clock~inputclkctrl , clock~inputclkctrl, rom2627, 1
instance = comp, \address[0]~input , address[0]~input, rom2627, 1
instance = comp, \address[1]~input , address[1]~input, rom2627, 1
instance = comp, \address[2]~input , address[2]~input, rom2627, 1
instance = comp, \address[3]~input , address[3]~input, rom2627, 1
instance = comp, \address[4]~input , address[4]~input, rom2627, 1
instance = comp, \address[5]~input , address[5]~input, rom2627, 1
instance = comp, \inst|srom|rom_block|auto_generated|ram_block1a0 , inst|srom|rom_block|auto_generated|ram_block1a0, rom2627, 1
design_name = hard_block
instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1
instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1
instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1