EDA Netlist Writer report for timing2627 Tue Oct 24 15:45:21 2023 Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. EDA Netlist Writer Summary 3. Simulation Settings 4. Simulation Generated Files 5. EDA Netlist Writer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2017 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ ; EDA Netlist Writer Status ; Successful - Tue Oct 24 15:45:21 2023 ; ; Revision Name ; timing2627 ; ; Top-level Entity Name ; timing2627 ; ; Family ; Cyclone IV E ; ; Simulation Files Creation ; Successful ; +---------------------------+---------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------+ ; Simulation Settings ; +---------------------------------------------------------------------------------------------------+---------------------------+ ; Option ; Setting ; +---------------------------------------------------------------------------------------------------+---------------------------+ ; Tool Name ; ModelSim-Altera (Verilog) ; ; Generate functional simulation netlist ; On ; ; Truncate long hierarchy paths ; Off ; ; Map illegal HDL characters ; Off ; ; Flatten buses into individual nodes ; Off ; ; Maintain hierarchy ; Off ; ; Bring out device-wide set/reset signals as ports ; Off ; ; Enable glitch filtering ; Off ; ; Do not write top level VHDL entity ; Off ; ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; ; Architecture name in VHDL output netlist ; structure ; ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; ; Generate third-party EDA tool command script for gate-level simulation ; Off ; +---------------------------------------------------------------------------------------------------+---------------------------+ +-----------------------------------------------------------+ ; Simulation Generated Files ; +-----------------------------------------------------------+ ; Generated Files ; +-----------------------------------------------------------+ ; D:/Projects/quartus/timing/simulation/qsim//timing2627.vo ; +-----------------------------------------------------------+ +-----------------------------+ ; EDA Netlist Writer Messages ; +-----------------------------+ Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Oct 24 15:45:21 2023 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=D:/Projects/quartus/timing/simulation/qsim/ timing2627 -c timing2627 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file timing2627.vo in folder "D:/Projects/quartus/timing/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4632 megabytes Info: Processing ended: Tue Oct 24 15:45:21 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:01