$comment
	File created using the following command:
		vcd file Timig2627.msim.vcd -direction
$end
$date
	Fri Oct 20 16:03:14 2023
$end
$version
	ModelSim Version 10.5b
$end
$timescale
	1ps
$end

$scope module Timig2627_vlg_vec_tst $end
$var reg 1 ! CLK1 $end
$var reg 1 " RST1 $end
$var reg 1 # s0 $end
$var wire 1 $ T1 $end
$var wire 1 % T2 $end
$var wire 1 & T3 $end
$var wire 1 ' T4 $end

$scope module i1 $end
$var wire 1 ( gnd $end
$var wire 1 ) vcc $end
$var wire 1 * unknown $end
$var tri1 1 + devclrn $end
$var tri1 1 , devpor $end
$var tri1 1 - devoe $end
$var wire 1 . T1~output_o $end
$var wire 1 / T4~output_o $end
$var wire 1 0 T3~output_o $end
$var wire 1 1 T2~output_o $end
$var wire 1 2 s0~input_o $end
$var wire 1 3 inst5~feeder_combout $end
$var wire 1 4 RST1~input_o $end
$var wire 1 5 RST1~inputclkctrl_outclk $end
$var wire 1 6 inst5~q $end
$var wire 1 7 inst6~feeder_combout $end
$var wire 1 8 inst6~q $end
$var wire 1 9 inst7~feeder_combout $end
$var wire 1 : inst7~q $end
$var wire 1 ; inst8~q $end
$var wire 1 < CLK1~input_o $end
$var wire 1 = ins10t~combout $end
$var wire 1 > ins10t~clkctrl_outclk $end
$var wire 1 ? inst3|5~0_combout $end
$var wire 1 @ inst3|5~1_combout $end
$var wire 1 A inst4~q $end
$upscope $end
$upscope $end
$enddefinitions $end
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