vendor_name = ModelSim
source_file = 1, F:/2/Timig2627.bdf
source_file = 1, c:/intelfpga_lite/17.1/quartus/libraries/others/maxplus2/21mux.bdf
design_name = Timig2627
instance = comp, \T1~output , T1~output, Timig2627, 1
instance = comp, \T4~output , T4~output, Timig2627, 1
instance = comp, \T3~output , T3~output, Timig2627, 1
instance = comp, \T2~output , T2~output, Timig2627, 1
instance = comp, \s0~input , s0~input, Timig2627, 1
instance = comp, \inst5~feeder , inst5~feeder, Timig2627, 1
instance = comp, \RST1~input , RST1~input, Timig2627, 1
instance = comp, \RST1~inputclkctrl , RST1~inputclkctrl, Timig2627, 1
instance = comp, \inst6~feeder , inst6~feeder, Timig2627, 1
instance = comp, \inst7~feeder , inst7~feeder, Timig2627, 1
instance = comp, \CLK1~input , CLK1~input, Timig2627, 1
instance = comp, \ins10t~clkctrl , ins10t~clkctrl, Timig2627, 1
instance = comp, \inst3|5~0 , inst3|5~0, Timig2627, 1
instance = comp, \inst3|5~1 , inst3|5~1, Timig2627, 1
design_name = hard_block
instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1
instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1
instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1