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// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/24/2023 15:45:20"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          timing2627
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module timing2627_vlg_vec_tst();
// constants                                           
// general purpose registers
reg CLK1;
reg RST1;
reg s0;
// wires                                               
wire debug_clk;
wire debug_D;
wire T1;
wire T2;
wire T3;
wire T4;

// assign statements (if any)                          
timing2627 i1 (
// port map - connection between master ports and signals/registers   
	.CLK1(CLK1),
	.debug_clk(debug_clk),
	.debug_D(debug_D),
	.RST1(RST1),
	.s0(s0),
	.T1(T1),
	.T2(T2),
	.T3(T3),
	.T4(T4)
);
initial 
begin 
#640000 $finish;
end 

// RST1
initial
begin
	RST1 = 1'b0;
	RST1 = #20000 1'b1;
	RST1 = #50000 1'b0;
	RST1 = #10000 1'b1;
	RST1 = #80000 1'b0;
	RST1 = #10000 1'b1;
	RST1 = #160000 1'b0;
	RST1 = #70000 1'b1;
	RST1 = #140000 1'b0;
	RST1 = #20000 1'b1;
	RST1 = #50000 1'b0;
	RST1 = #20000 1'b1;
end 

// CLK1
initial
begin
	repeat(21)
	begin
		CLK1 = 1'b0;
		CLK1 = #10000 1'b1;
		# 10000;
	end
	repeat(5)
	begin
		CLK1 = 1'b0;
		CLK1 = #10000 1'b1;
		# 10000;
	end
	CLK1 = 1'b0;
	CLK1 = #10000 1'b1;
	# 10000;
	repeat(5)
	begin
		CLK1 = 1'b0;
		CLK1 = #10000 1'b1;
		# 10000;
	end
end 

// s0
initial
begin
	s0 = 1'b1;
	s0 = #320000 1'b0;
end 
endmodule